Renesas H8SX/1650, Hardware Manual

Page: 144 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 122 of 666
REJ09B0311-0200
•
Idle cycle insertion
Idle cycles can be inserted between external read accesses to different areas.
Idle cycles can be inserted before the external write access after an external read access.
Idle cycles can be inserted before the external read access after an external write access.
•
Write buffer function
External write cycles and internal accesses can be executed in parallel
Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed
in parallel
•
External bus release function
•
Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC
•
Multi-clock function
The internal peripheral functions can be operated in synchronization with the peripheral
module clock (P
φ
). Accesses to the external address space can be operated in synchronization
with the external bus clock (B
φ
).
•
The bus start (
BS
) and read/write (RD/
WR
) signals can be output.