Renesas H8SX/1650, Hardware Manual

Page: 335 / 692

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.2.00 Jun. 28, 2007 Page 313 of 666
REJ09B0311-0200
Table 9.3 CCLR2 to CCLR0 (Channels 0 and 3)
Channel
Bit 7
CCLR2 Bit 6
CCLR1 Bit 5
CCLR0 Description
0 0 0 TCNT clearing disabled
0 0 1 TCNT cleared by TGRA compare match/input
capture
0 1 0 TCNT cleared by TGRB compare match/input
capture
0 1 1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
1 0 0 TCNT clearing disabled
1 0 1 TCNT cleared by TGRC compare match/input
capture
*
2
1 1 0 TCNT cleared by TGRD compare match/input
capture
*
2
0, 3
1 1 1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.