Renesas H8SX/1650, Hardware Manual

Page: 32 / 692

Section 1 Overview
Rev.2.00 Jun. 28, 2007 Page 10 of 666
REJ09B0311-0200
1.5 Pin Functions
Table 1.3 Pin Functions
Classification Pin Name I/O Description
Power supply V
CC

Power supply pins. Connect them to the system power
supply.
V
CL

Connect this pin to V
SS
via a 0.1-uF capacitor (The capacitor
should be placed close to the pin).
V
SS

Ground pins. Connect them to the system power supply
(0 V).
PLLV
CC

Power supply pin for the PLL circuit.
PLLV
SS

Ground pin for the PLL circuit.
Clock XTAL Input
EXTAL Input
Pins for a crystal resonator. An external clock signal can be
input through the EXTAL pin. For an example of this
connection, see section 17, Clock Pulse Generator.
B
φ
Output Outputs the system clock for external devices.
Operating mode
control MD2 to MD0 Input Pins for setting the operating mode. The signal levels on
these pins must not be changed during operation.
System control
RES
Input Reset signal input pin. This LSI enters the reset state when
this signal goes low.
STBY
Input This LSI enters hardware standby mode when this signal
goes low.
EMLE Input Input pin for the on-chip emulator enable signal. The signal
level should normally be fixed low.
Address bus A23 to A0 Output Output pins for the address bits.
Data bus D15 to D0 Input/
output Input and output for the bidirectional data bus. These pins
also output addresses when accessing an address–data
multiplexed I/O interface space.
Bus control
BREQ
Input External bus-master modules assert this signal to request
the bus.
BREQO
Output Internal bus-master modules assert this signal to request
access to the external space via the bus in the external bus
released state.