Renesas H8SX/1650, Hardware Manual

Page: 249 / 692

Section 7 Data Transfer Controller (DTC)
Rev.2.00 Jun. 28, 2007 Page 227 of 666
REJ09B0311-0200
Bit Bit Name
Initial
Value R/W Description
0 ERR 0 R/(W) * Transfer Stop Flag
Indicates that an address error or an NMI interrupt
occurs. If an address error or an NMI interrupt occurs, the
DTC stops.
0: No interrupt occurs
1: An interrupt occurs
[Clearing condition]
•
When writing 0 after reading 1
Note: * Only 0 can be written to clear this flag.
7.2.9 DTC Vector Base Register (DTCVBR)
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.
Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is
H'00000000.
Bit
Bit Name
Initial Value
R/W
31
0
R
30
0
R
29
0
R
28
0
R
27
0
R/W
26
0
R/W
25
0
R/W
24
0
R/W
23
0
R/W
22
0
R/W
21
0
R/W
20
0
R/W
19
0
R/W
18
0
R/W
17
0
R/W
16
0
R/W
Bit
Bit Name
Initial Value
R/W
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R
10
0
R
9
0
R
8
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
7.3 Activation Sources
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.