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Section 18 Power-Down States
Rev.2.00 Jun. 28, 2007 Page 580 of 666
REJ09B0311-0200
18.8
Hardware Standby Mode
18.8.1
Transition to Hardware Standby Mode
When the
STBY
pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the
STBY
pin low. Do not change the state of the mode pins (MD2 to MD0) while this
LSI is in hardware standby mode.
18.8.2 Clearing
Hardware Standby Mode
Hardware standby mode is cleared by means of the
STBY
pin and the
RES
pin. When the
STBY
pin is driven high while the
RES
pin is low, the reset state is entered and clock oscillation is
started. Ensure that the
RES
pin is held low until clock oscillation settles (for details on the
oscillation settling time, refer to table 18.2). When the
RES
pin is subsequently driven high, a
transition is made to the program execution state via the reset exception handling state.
18.8.3
Hardware Standby Mode Timing
Figure 18.3 shows an example of hardware standby mode timing.
When the
STBY
pin is driven low after the
RES
pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the
STBY
pin high,
waiting for the oscillation settling time, then changing the
RES
pin from low to high.
Oscillator
RES
STBY
Oscillation
settling time
Reset
exception handling
Figure 18.3 Hardware Standby Mode Timing
Summary of Contents for H8SX/1650
Page 2: ...Rev 2 00 Jun 28 2007 Page ii of xxii...
Page 106: ...Section 4 Exception Handling Rev 2 00 Jun 28 2007 Page 84 of 666 REJ09B0311 0200...
Page 142: ...Section 5 Interrupt Controller Rev 2 00 Jun 28 2007 Page 120 of 666 REJ09B0311 0200...
Page 326: ...Section 8 I O Ports Rev 2 00 Jun 28 2007 Page 304 of 666 REJ09B0311 0200...
Page 470: ...Section 12 Watchdog Timer WDT Rev 2 00 Jun 28 2007 Page 448 of 666 REJ09B0311 0200...
Page 566: ...Section 14 A D Converter Rev 2 00 Jun 28 2007 Page 544 of 666 REJ09B0311 0200...
Page 574: ...Section 16 RAM Rev 2 00 Jun 28 2007 Page 552 of 666 REJ09B0311 0200...
Page 584: ...Section 17 Clock Pulse Generator Rev 2 00 Jun 28 2007 Page 562 of 666 REJ09B0311 0200...
Page 638: ...Section 19 List of Registers Rev 2 00 Jun 28 2007 Page 616 of 666 REJ09B0311 0200...
Page 668: ...Section 20 Electrical Characteristics Rev 2 00 Jun 28 2007 Page 646 of 666 REJ09B0311 0200...
Page 676: ...Appendix Rev 2 00 Jun 28 2007 Page 654 of 666 REJ09B0311 0200...
Page 688: ...Rev 2 00 Jun 28 2007 Page 666 of 666 REJ09B0311 0200...
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Page 692: ...H8SX 1650 Group Hardware Manual...