Renesas H8SX/1650, Hardware Manual

Page: 487 / 692

Section 13 Serial Communication Interface (SCI)
Rev.2.00 Jun. 28, 2007 Page 465 of 666
REJ09B0311-0200
Bit Bit Name
Initial
Value R/W Description
4 FER 0 R/(W) * Framing Error
Indicates that a framing error has occurred during
reception in asynchronous mode and the reception
ends abnormally.
[Setting condition]
•
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is checked
whether it is 1 but the second stop bit is not
checked. Note that receive data when the framing
error occurs is transferred to RDR, however, the
RDRF flag is not set. In addition, when the FER flag
is being set to 1, the subsequent serial reception
cannot be performed. In clocked synchronous
mode, serial transmission also cannot continue.
[Clearing condition]
•
When 0 is written to FER after reading FER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the FER
flag is not affected and retains its previous value.
3 PER 0 R/(W) * Parity Error
Indicates that a parity error has occurred during
reception in asynchronous mode and the reception
ends abnormally.
[Setting condition]
•
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1,
the subsequent serial reception cannot be
performed. In clocked synchronous mode, serial
transmission also cannot continue.
[Clearing condition]
•
When 0 is written to PER after reading PER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the PER
bit is not affected and retains its previous value.