Renesas H8SX/1650, Hardware Manual

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Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 202 of 666
REJ09B0311-0200
(3)
Read after Write
If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7).
Figure 6.36 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted,
and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM
device. In (b), an idle cycle is inserted, and a data conflict is prevented.
Output floating time is large
Data conflict
Bus cycle A Bus cycle B
B
φ
Address bus
CS
(area A)
CS
(area B)
RD
LLWR
Data bus
T
1
T
2
T
3
T
1
T
2
Bus cycle A Bus cycle B
T
1
T
2
T
3
T
1
T
i
T
2
(a) No idle cycle inserted
(IDLS2 = 0)
(b) Idle cycle inserted
(IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0)
Figure 6.36 Example of Idle Cycle Operation (Read after Write)