Renesas H8SX/1650, Hardware Manual

Page: 587 / 692

Section 18 Power-Down States
Rev.2.00 Jun. 28, 2007 Page 565 of 666
REJ09B0311-0200
SLEEP
instruction
*
3
SLEEP
instruction
*
3
All interrupts
SLEEP instruction
*
3
External
interrupt
*
2
Interrupt *
1
RES
pin = low
STBY
pin = high
STBY
pin = low
SSBY = 0
SSBY = 0, ACSE = 1
MSTPCR = H'F[0-F]FFFFFF
SSBY = 1
RES
pin = high
Transition after exception handling
Reset state
Program execution state
Program halted state
Hardware standby mode
Sleep mode
Notes: 1. NMI,
IRQ0
to
IRQ11
, 8-bit timer interrupts, and watchdog timer interrupts.
The 8-bit timer is valid when bits MSTPCRA11 to MSTPCRA8 are all cleared to 0.
2. NMI and
IRQ0
to
IRQ11
. Note that IRQ is valid only when the corresponding bit in SSIER is set to 1.
From any state, a transition to hardware standby mode occurs when
STBY
is driven low.
From any state except for hardware standby mode, a transition to the reset state occurs when
RES
is driven low.
3. When the SLPIE bit is cleared to 0
All-module-clock-
stop mode
Software standby mode
Figure 18.1 Mode Transitions
18.2 Register Descriptions
The registers related to the power-down state are shown below. For details on the system clock
control register (SCKCR), see section 17.1.1, System Clock Control Register (SCKCR).
•
Standby control register (SBYCR)
•
Module stop control register A (MSTPCRA)
•
Module stop control register B (MSTPCRB)
•
Module stop control register C (MSTPCRC)