Renesas H8SX/1650, Hardware Manual

Page: 179 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 157 of 666
REJ09B0311-0200
(4)
Number of Access Cycles
(a)
Basic Bus Interface
The number of access cycles in the basic bus interface can be specified as two or three cycles by
the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area
specified as 3-state access is specified as 3-state access space.
For the 2-state access space, a wait cycle insertion is disabled. For the 3-state access space, a
program wait (0 to 7 cycles) specified by WTCRA and WTCRB or an external wait by
WAIT
can
be inserted.
In addition, CSACR can extend the assert periods of the chip select signal and address signal.
Number of access cycles in the basic bus interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
+ number of
CS
extension cycles (0, 1, 2)
[+ number of external wait cycles by the
WAIT
pin]
(b)
Byte Control SRAM Interface
The number of access cycles in the byte control SRAM interface is the same as that in the basic
bus interface.
Number of access cycles in byte control SRAM interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
+ number of
CS
extension cycles (0, 1, 2)
[+ number of external wait cycles by the
WAIT
pin]
(c)
Burst ROM Interface
The number of access cycles at full access in the burst ROM interface is the same as that in the
basic bus interface. The number of access cycles in the burst access can be specified as one to
eight cycles by the BSTS bit in BROMCR.
Number of access cycles in the burst ROM interface
= number of basic cycles (2, 3) + number of program wait cycles (0 to 7)
+ number of
CS
extension cycles (0, 1)
[+number of external wait cycles by the
WAIT
pin]
+ number of burst access cycles (1 to 8)
×
number of burst accesses (0 to 63)