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Section 2
CPU
Rev.2.00 Jun. 28, 2007 Page 59 of 666
REJ09B0311-0200
2.9 Processing
States
The H8SX CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and program stop state. Figure 2.16 indicates the state
transitions.
•
Reset state
In this state the CPU and internal peripheral modules are all initialized and stopped. When the
RES
input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the
RES
signal
changes from low to high. For details, see section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow when available.
•
Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or
trap instruction. The CPU fetches a start address (vector) from the exception handling vector
table and branches to that address. For further details, see section 4, Exception Handling.
•
Program execution state
In this state the CPU executes program instructions in sequence.
•
Bus-released state
The bus-released state occurs when the bus has been released in response to a bus request from
a bus master other than the CPU. While the bus is released, the CPU halts operations.
•
Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
see section 18, Power-Down States.
Summary of Contents for H8SX/1650
Page 2: ...Rev 2 00 Jun 28 2007 Page ii of xxii...
Page 106: ...Section 4 Exception Handling Rev 2 00 Jun 28 2007 Page 84 of 666 REJ09B0311 0200...
Page 142: ...Section 5 Interrupt Controller Rev 2 00 Jun 28 2007 Page 120 of 666 REJ09B0311 0200...
Page 326: ...Section 8 I O Ports Rev 2 00 Jun 28 2007 Page 304 of 666 REJ09B0311 0200...
Page 470: ...Section 12 Watchdog Timer WDT Rev 2 00 Jun 28 2007 Page 448 of 666 REJ09B0311 0200...
Page 566: ...Section 14 A D Converter Rev 2 00 Jun 28 2007 Page 544 of 666 REJ09B0311 0200...
Page 574: ...Section 16 RAM Rev 2 00 Jun 28 2007 Page 552 of 666 REJ09B0311 0200...
Page 584: ...Section 17 Clock Pulse Generator Rev 2 00 Jun 28 2007 Page 562 of 666 REJ09B0311 0200...
Page 638: ...Section 19 List of Registers Rev 2 00 Jun 28 2007 Page 616 of 666 REJ09B0311 0200...
Page 668: ...Section 20 Electrical Characteristics Rev 2 00 Jun 28 2007 Page 646 of 666 REJ09B0311 0200...
Page 676: ...Appendix Rev 2 00 Jun 28 2007 Page 654 of 666 REJ09B0311 0200...
Page 688: ...Rev 2 00 Jun 28 2007 Page 666 of 666 REJ09B0311 0200...
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