Renesas H8SX/1650, Hardware Manual

Page: 156 / 692

Section 6 Bus Controller (BSC)
Rev.2.00 Jun. 28, 2007 Page 134 of 666
REJ09B0311-0200
Bit Bit Name
Initial
Value R/W Description
15
14
13
12
11
10
9
8
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS
and Address Signal Assertion Period Control 1
These bits specify whether or not the Th cycle is to be
inserted (see figure 6.3). When an area for which bit
CSXHn is set to 1 is accessed, one Th cycle, in which the
CSn
and address signals are asserted, is inserted before
the normal access cycle.
0: In access to area n, the
CSn
and address assertion
period (Th) is not extended
1: In access to area n, the
CSn
and address assertion
period (Th) is extended
(n = 7 to 0)
7
6
5
4
3
2
1
0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CS
and Address Signal Assertion Period Control 2
These bits specify whether or not the Tt cycle is to be
inserted (see figure 6.3). When an area for which bit
CSXTn is set to 1 is accessed, one Tt cycle, in which the
CSn
and address signals are retained, is inserted after
the normal access cycle.
0: In access to area n, the
CSn
and address assertion
period (Tt) is not extended
1: In access to area n, the
CSn
and address assertion
period (Tt) is extended
(n = 7 to 0)
Note: * In burst ROM interface, the CSXTn settings are ignored.