Renesas H8SX/1650, Hardware Manual

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Section 11 8-Bit Timers (TMR)
Rev.2.00 Jun. 28, 2007 Page 432 of 666
REJ09B0311-0200
11.8 Usage Notes
11.8.1 Notes on Setting Cycle
If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in
which the values of TCNT and TCOR match. TCNT updates the counter value at this last state.
Therefore, the counter frequency is obtained by the following formula.
f =
φ
/ (N + 1 )
f: Counter frequency
φ
: Operating frequency
N: TCOR value
11.8.2 Conflict between TCNT Write and Clear
If a counter clear signal is generated during the T
2
state of a TCNT write cycle, the clear takes
priority and the write is not performed as shown in figure 11.13.
P
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 11.13 Conflict between TCNT Write and Clear