Section 14
A/D Converter
Rev.2.00 Jun. 28, 2007 Page 533 of 666
REJ09B0311-0200
ADIE
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Channel 2 (AN2)
operation state
Channel 3 (AN3)
operation state
Set
*
Set
*
Set
*
A/D conversion start
Clear
*
Clear
*
Waiting for conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
Reading A/D conversion result
Reading A/D conversion result
A/D conversion 1
A/D conversion 2
A/D conversion result 1
A/D conversion result 2
Waiting for
conversion
Note:
*
↓
indicates the timing of instruction execution by software.
Figure 14.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
14.4.2 Scan
Mode
In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified
channels up to four or eight channels.
1. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger
input, A/D conversion starts on the first channel in the group. Consecutive A/D conversion on
a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight
channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is
performed on four channels, A/D conversion starts on AN4 when CH3 and CH2 = B'01. When
consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0
when CH3 = B'0.
2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
transferred to the corresponding ADDR of each channel.
Summary of Contents for H8SX/1650
Page 2: ...Rev 2 00 Jun 28 2007 Page ii of xxii...
Page 106: ...Section 4 Exception Handling Rev 2 00 Jun 28 2007 Page 84 of 666 REJ09B0311 0200...
Page 142: ...Section 5 Interrupt Controller Rev 2 00 Jun 28 2007 Page 120 of 666 REJ09B0311 0200...
Page 326: ...Section 8 I O Ports Rev 2 00 Jun 28 2007 Page 304 of 666 REJ09B0311 0200...
Page 470: ...Section 12 Watchdog Timer WDT Rev 2 00 Jun 28 2007 Page 448 of 666 REJ09B0311 0200...
Page 566: ...Section 14 A D Converter Rev 2 00 Jun 28 2007 Page 544 of 666 REJ09B0311 0200...
Page 574: ...Section 16 RAM Rev 2 00 Jun 28 2007 Page 552 of 666 REJ09B0311 0200...
Page 584: ...Section 17 Clock Pulse Generator Rev 2 00 Jun 28 2007 Page 562 of 666 REJ09B0311 0200...
Page 638: ...Section 19 List of Registers Rev 2 00 Jun 28 2007 Page 616 of 666 REJ09B0311 0200...
Page 668: ...Section 20 Electrical Characteristics Rev 2 00 Jun 28 2007 Page 646 of 666 REJ09B0311 0200...
Page 676: ...Appendix Rev 2 00 Jun 28 2007 Page 654 of 666 REJ09B0311 0200...
Page 688: ...Rev 2 00 Jun 28 2007 Page 666 of 666 REJ09B0311 0200...
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Page 692: ...H8SX 1650 Group Hardware Manual...