Renesas H8SX/1650, Hardware Manual

Page: 588 / 692

Section 18 Power-Down States
Rev.2.00 Jun. 28, 2007 Page 566 of 666
REJ09B0311-0200
18.2.1 Standby Control Register (SBYCR)
SBYCR controls software standby mode.
Bit
Bit Name
Initial Value
R/W
15
SSBY
0
R/W
14
OPE
1
R/W
13

0
R/W
12
STS4
0
R/W
11
STS3
1
R/W
10
STS2
1
R/W
9
STS1
1
R/W
8
STS0
1
R/W
Bit
Bit Name
Initial Value
R/W
7
SLPIE
0
R/W
6

0
R/W
5

0
R/W
4

0
R/W
3

0
R/W
2

0
R/W
1

0
R/W
0

0
R/W
Bit Bit Name
Initial
Value R/W Description
15 SSBY 0 R/W Software Standby
Specifies the transition mode after executing the SLEEP
instruction
0: Shifts to sleep mode after the SLEEP instruction is
executed
1: Shifts to software standby mode after the SLEEP
instruction is executed
This bit does not change when clearing the software
standby mode by using external interrupts and shifting to
normal operation. For clearing, write 0 to this bit. When
the WDT is used as the watchdog timer, the setting of this
bit is disabled. In this case, a transition is always made to
sleep mode or all-module-clock-stop mode after the
SLEEP instruction is executed.
This bit should be cleared to 0 when setting the SLPIE bit
to 1.
14 OPE 1 R/W Output Port Enable
Specifies whether the output of the address bus and bus
control signals (
CS0
to
CS7
,
AS
,
RD
,
HWR
, and
LWR
) is
retained or set to the high-impedance state in software
standby mode.
0: In software standby mode, address bus and bus
control signals are high-impedance
1: In software standby mode, address bus and bus
control signals retain output state