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4-5-1 TR Bits
The TR area provides eight bits, TR0 through TR7, that can be used to tempo-
rarily preserve execution conditions. If a TR bit is placed at a branching point, the
current execution condition will be stored at the designated TR bit. When return-
ing to the branching point, the TR bit restores the execution status that was
saved when the branching point was first reached in program execution.
Note When programming in graphic ladder diagram form from the SSS, it is not nec-
essary to input TR bits and none will appear on the screen. The SSS will auto-
matically process TR bits for you as required and input them into the program.
You will have to input TR bit when programming in mnemonic form.
The previous diagram B can be written as shown below to ensure correct execu-
tion. In mnemonic code, the execution condition is stored at the branching point
using the TR bit as the operand of the OUTPUT instruction. This execution
condition is then restored after executing the right-hand instruction by using the
same TR bit as the operand of a LOAD instruction.
Diagram B: Corrected Using a TR bit
TR0
Address
Instruction
00000
LD
000000
00001
OUT
TR0
00002
AND
000001
00003
Instruction 1
00004
LD
TR0
00005
AND
000002
00006
Instruction 2
Operands
0000
00
0000
02
0000
01
Instruction 2
Instruction 1
In terms of actual instructions the above diagram would be as follows: The status
of CIO 000000 is loaded (a LOAD instruction) to establish the initial execution
condition. This execution condition is then output using an OUTPUT instruction
to TR0 to store the execution condition at the branching point. The execution
condition is then ANDed with the status of CIO 000001 and instruction 1 is
executed accordingly. The execution condition that was stored at the branching
point is then re-loaded (a LOAD instruction with TR0 as the operand), this is
ANDed with the status of CIO 000002, and instruction 2 is executed accordingly.
The following example shows an application using two TR bits.
Address
Instruction
00000
LD
000000
00001
OUT
TR0
00002
AND
000001
00003
OUT
TR1
00004
AND
000002
00005
OUT
000500
00006
LD
TR1
00007
AND
000003
00008
OUT
000501
00009
LD
TR0
00010
AND
000004
00011
OUT
000502
00012
LD
TR0
00013
AND NOT
000005
00014
OUT
000503
Operands
0000
05
0000
00
0000
01
0000
02
0000
03
0000
04
0005
00
0005
01
0005
02
0005
03
TR0
TR1
Branching Instruction Lines
Section 4-5
Summary of Contents for CVM1D
Page 462: ...SYSMAC CVM1D Duplex System Programmable Controllers Operation Manual Revised August 2001...
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