Omron CVM1D, Operation Manual

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71
When AND and OR instructions are combined in more complicated diagrams,
they can sometimes be considered individually, with each instruction performing
a logic operation on the current execution condition and the status of the oper-
and bit. The following is one example. Study this example until you are con-
vinced that the mnemonic code follows the same logic flow as the ladder dia-
gram.
Instruction
0000
03
0000
00
0000
01
0000
02
0002
00
Address Instruction Operands
00000 LD 000000
00001 AND 000001
00002 OR 000200
00003 AND 000002
00004 AND NOT 000003
00005 Instruction
Here, an AND is taken between the status of CIO 000000 and that of
CIO 000001 to determine the execution condition for an OR with the status of
CIO 000200. The result of this operation determines the execution condition for
an AND with the status of CIO 000002, which in turn determines the execution
condition for an AND with the inverse (i.e., and AND NOT) of the status of
CIO 000003.
In more complicated diagrams, it is necessary to consider logic blocks before an
execution condition can be determined for the final instruction, and that’s where
AND LOAD and OR LOAD instructions are used. Before we consider more com-
plicated diagrams, however, we’ll look at the instructions required to complete a
simple “input-output” program.
4-3-4 OUTPUT and OUTPUT NOT
The simplest way to output the results of combining execution conditions is to
output it directly with the OUTPUT and OUTPUT NOT. These instructions are
used to control the status of the designated operand bit according to the execu-
tion condition. With the OUTPUT instruction, the operand bit will be turned ON
as long as the execution condition is ON and will be turned OFF as long as the
execution condition is OFF. With the OUTPUT NOT instruction, the operand bit
will be turned ON as long as the execution condition is OFF and turned OFF as
long as the execution condition is ON. These appear as shown below. In mne-
monic code, each of these instructions requires one line.
Address Instruction Operands
00000 LD 000000
00001 OUT 000200
Address Instruction Operands
00000 LD 000001
00001 OUT NOT 000201
0002
00
0002
01
0000
00
0000
01
In the above examples, CIO 000200 will be ON as long as CIO 000000 is ON and
CIO 000201 will be ON as long as CIO 000001 is OFF. Here, CIO 000000 and
CIO 000001 would be input bits and CIO 000200 and CIO 000201 output bits
assigned to the Units controlled by the PC, i.e., the signals coming in through the
input points assigned CIO 000000 and CIO 000001 are controlling the output
points to which CIO 000200 and CIO 000201 are allocated.
The length of time that a bit is ON or OFF can be controlled by combining the
OUTPUT or OUTPUT NOT instruction with Timer instructions. Refer to Exam-
ples under 5-13-1 Timer – TIM for details.
Combining AND and OR
Instructions
Basic Ladder Diagrams
Section 4-3