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The data in the following table is used to produce the minimum and maximum
cycle times shown calculated below.
Input ON delay
1.5 ms
Cycle time
20 ms
Output ON delay
15 ms
Communications cycle time
5 ms (one group 3, 58M Slave)
The PC responds most quickly when it receives an input signal just prior to SYS-
MAC BUS/2 refreshing.
Input signal
Output signal
Cycle
Cycle time
I/O refresh
I/O response time
Output ON delay
Input ON delay
Buffer in Master
A
B
A: Program execution
B: Programming Device
servicing
A
B
A
B
Minimum I/O response time = input ON delay
+ communications cycle time
×(
5+ cycle time x 2
+ output ON delay
Minimum I/O response time = 1.5 + (5
×
5) + (20
×
2) +15 = 81.5 ms
The PC takes longest to respond when it receives the input signal just after SYS-
MAC BUS/2 refreshing. In this case the CPU does not recognize the input signal
until the next cycle. This situation is illustrated below.
Input signal
Output signal
Cycle
Cycle time
I/O refresh
I/O response time
Output ON delay
Input ON delay
Buffer in Master
A
B
A: Program execution
B: Programming Device
servicing
A
B
A
B
A
Maximum I/O response time = input ON delay
+ communications cycle time
×(
7 + cycle time
×(
3
+ 10 ms + output ON delay
Maximum I/O response time = 1.5 + (5
×
7) + (20
×
3) +10 +15 = 121.5 ms
Minimum I/O Response
Time
Maximum I/O Response
Time
I/O Response Time
Section 6-5
Summary of Contents for CVM1D
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