MAX32600 User’s Guide
Introduction
2.7 Digital Peripherals
The first watchdog instance (WDT0) can be configured to trigger a system reset (reset of digital core) when it generates a watchdog reset. The second watchdog
instance (WDT1) can be configured to generate a system reboot (equivalent to digital POR event) when it generates a watchdog reset.
The two watchdogs may be configured independently to use either the currently selected system clock or an external clock as the watchdog clock source. The
external clock is selected separately (in system manager) and is the same for both watchdog instances.
2.7.4
32-Bit Real Time Clock with Time of Day Alarm
A binary real-time clock (RTC) keeps the time of day in absolute seconds with 1/256-second resolution. The 32-bit second counter can count up to approximately
140 years and be translated to calendar format by application software. A time-of-day alarm and independent sub-second alarm can cause an interrupt or wake the
device from stop mode.
The independent sub-second alarm runs from the same RTC and allows the application to support interrupts with a minimum interval of approximately 3.9ms. This
creates an additional timer that can be used to measure long periods of time without performance degradation.
2.7.5
SPI (three instances)
The integrated SPI controller provides an independent master-mode-only serial communication channel that communicates synchronously with peripheral devices in
a single or multiple slave system. Depending on the other peripherals and GPIO pins that are in use by the application, up to two separate SPI ports are available for
general use, with a third SPI instance reserved for Bluetooth module communication.
The SPI controllers support half- or full-duplex communications with single, dual, or quad data transmission modes, and can be operated in master mode only.In
master mode, the SPI can transfer data at up to 24 MHz depending on the clock source. In addition, the SPI module supports configuration of active SSEL state
(active low or active high) through the slave active select. DMA is supported for both the transmit and receive buffers.
2.7.6
I²C
The microcontroller integrates an internal I
2
C bus master/slave for communication with a wide variety of other I
2
C-enabled peripherals. The I
2
C bus is a two-wire,
bidirectional bus using a ground line and two bus lines: the serial data line (SDA) and the serial clock line (SCL). Both the SDA and SCL lines must be driven as
open-collector/drain outputs. External resistors (R
P
) are required to pull the lines to a logic-high state.
The device supports both the master and slave protocols. In the master mode, the device has ownership of the I
2
C bus, drives the clock, and generates the START
and STOP signals. This allows it to send data to a slave or receive data from a slave as required. In slave mode, the device relies on an externally generated clock
to drive SCL and responds to data and commands only when requested by the I
2
C master device.
There are two instances of the I
2
C master interface and one instance of the I
2
C slave interface supported.
Rev.1.3 April 2015
Maxim Integrated
Page 19
