MAX32600 User’s Guide
System Clock, Timers/Counters, Watchdog Timers and Real Time Clock
10.1 System Clock
• 0: Disabled
• 1: Enable the 8MHz output of the PLL
CLKMAN_CLK_CONFIG.pll_bypass
Field
Bits
Default
Access
Description
pll_bypass
19
no effect
R/W
Reserved Field; Do Not Modify
This register field must be left at its default value for proper operation.
CLKMAN_CLK_CONFIG.pll_stability_count
Field
Bits
Default
Access
Description
pll_stability_count
23:20
no effect
R/W
PLL Stability Count Select
Defines terminal count for PLL stable indicator in terms of PLL clocks as (# of clocks) = 2
∧
(bits[23:20] + 8)
• 0000b: 256 clocks (2
∧
8)
• 0001b: 512 clocks (2
∧
9)
• 0010b: 1024 clocks (2
∧
10)
• ...
• 1110b: 4194304 clocks (2
∧
22)
• 1111b: 8388608 clocks (2
∧
23)
CLKMAN_CLK_CONFIG.crypto_enable
Rev.1.3 April 2015
Maxim Integrated
Page 515
