MAX32600 User’s Guide
Communication Peripherals
7
Communication Peripherals
7.1
I²C
7.1.1
I²C Overview
The
MAX32600
integrates two I
2
C bus masters for communication with a wide variety of I
2
C enabled slaves. The I
2
C bus is a two-wire, bidirectional bus (i.e., can
operate as a master-transmitter or master-receiver) using a ground line and two bus lines: the serial data access line (SDA) and the serial clock line (SCL). Both the
SDA and SCL lines must be driven as open-collector/drain outputs. External resistors (R
P
) are recommended to pull the lines to a logic-high state; internal pullups
can also be used to start I
2
C buses with low capacitance.
The device supports both the master and slave protocols. The master I
2
C peripherals have ownership of the I
2
C bus, drive the clock via the SCL pin, and generate
the START and STOP signals. This enables the
MAX32600
to send and receive data from a slave as required by the user’s application. In slave mode, the device
relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I
2
C master device.
7.1.2
I²C Features
The I
2
C host port is compliant with the I
2
C Bus Specification with features:
• I
2
C bus specification version 2.1 compliant (100kHz and 400kHz)
• Programmable for both normal (100 kHz) and fast bus data rates (400kHz)
• Tagged-byte (16-byte depth) FIFOs:
–
Transaction FIFO
–
Results FIFO
• Support for 10-bit device addressing
• Clock synchronization and bus arbitration
• Supports arbitration in a multi-master environment
• Supports I
2
C bus hold for slow host service
• Transfer status interrupts and flags
• Support DMA data transfer via the
Peripheral Management Unit (PMU)
The
MAX32600
I
2
C bus I²Cports the following FIFO slave features:
Rev.1.3 April 2015
Maxim Integrated
Page 216
