MAX32600 User’s Guide
Peripheral Management Unit (PMU)
6.3 PMU Programming Details
Figure 6.4: PMU WAIT Op Code Details
INT
• Set to 1 to generate an interrupt to the CPU upon completion of this op code.
STOP
• Set to 1 if this op code is to terminate op code processing after execution.
• This also clears the START bit field in the
register.
The interrupt mask field corresponds to the following interrupt sources available to the PMU from the
MAX32600
.
The following interrupts are generated by the Peripheral FIFOs automatically as listed below based on FIFO configuration registers. These interrupts
do not
require
the user to clear or enable the interrupt source, they are self clearing and enabled by the appropriate FIFO configuration registers as shown in the table below.
PMU FIFO Interrupt Sources - Peripheral FIFO Generated
Interrupt Bit
Source
Cause
0
DAC0 almost empty
Interrupt is set when FIFO level falls below user defined threshold in the
register field,
interrupt self-clears when the FIFO level is above the user defined threshold in
1
DAC1 almost empty
Interrupt is set when FIFO level falls below user defined threshold in the
register field,
interrupt self-clears when the FIFO level is above the user defined threshold in
Rev.1.3 April 2015
Maxim Integrated
Page 199
