Maxim Integrated MAX32600, User Manual

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MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.3 Real Time Clock (RTC)
4. The RTC can is now be enabled by setting RTCTMR_CTRL.enable bit to 1.
Turning on the RTC Block and 32kHz Crystal Oscillator
By default, the RTC block and the 32kHz crystal oscillator are disabled following an RTC POR event.
To enable RTC operation during LP2: PMU and LP3: RUN , set the power sequencer control bit PWRSEQ_REG0.pwr_rtcen_run to 1. Alternately, write 1 to PWRS
−
EQ_REG0.pwr_rtcen_slp to enable RTC operation during LP0: STOP and LP1: STANDBY . This will power on the RTC block and, based on the RTC POR default
setting of RTCCFG_OSC_CTRL , the RTC oscillator will be enabled to run as well.
Set the RTC timer to a zero starting value
• Write RTCTMR_TIMER to 00000000h.
• The RTCTMR_CTRL.pending status bit will change to 1 to indicate that a clock domain synchronization is pending; the bit will change back to 0 once the
synchronization has completed.
– Note : It is not necessary to wait for the pending bit to go low before writing to other RTC registers; this pending bit is most useful to signal when it is
permitted to go to LP0 or LP1.
If the RTC Time of Day Alarm will be used, set the appropriate compare register(s)
• Write RTCTMR_COMP0 or RTCTMR_COMP1 to the desired compare value.
• Perform a clear operation on one of the flags in RTCTMR_FLAGS to ensure the register write just performed is synchronized correctly.
• The RTCTMR_CTRL.pending status bit will change to 1 to indicate that clock domain synchronization is pending; the bit will change back to 0 once the
synchronization has completed.
Note After writing to any of the following registers: RTCTMR_COMP0 , RTCTMR_COMP1 , or RTCTMR_TRIM_VALUE , in order to ensure that the syn-
chronization to the 4kHz clock domain completes correctly, it is necessary to follow the register write with a separate write of a ’1’ value to the
RTCTMR_FLAGS register. (Any value can be used that results in a clear or attempted clear of any of the flags in bits [4:0] of this register, even if
none of the flags are set; the write is merely needed to trigger the synchronization process.)
Set the prescaler to the desired setting
• Write the RTCTMR_PRESCALE.width_selection field to the desired clock rate prescale setting.
Rev.1.3 April 2015 Maxim Integrated Page 566