Maxim Integrated MAX32600, User Manual, Page: 303 / 687

MAX32600 User’s Guide Communication Peripherals 7.3 UART
Logic Signal Port and Pin
RTS A) P1.3 B) P1.5 C) P7.3 D) P0.3
UART1
Logic Signal Port and Pin
RX A) P1.2 B) P1.4 C) P7.2 D) P2.6
TX A) P1.3 B) P1.5 C) P7.3 D) P2.7
CTS A) P2.6 B) P1.6 C) P7.6
RTS A) P2.7 B) P1.7 C) P7.7
7.3.3 Port Register Blocks
Each UART instance is controlled by a block of registers assigned to that port; all blocks contain identical control, interrupt, status, and FIFO read/write registers.
The addresses for each register block are shown in the table below.
Registers for UART0
Address Register Details
0x40038000 UART0_CTRL UART Control Register
0x40038004 UART0_STATUS UART Status Register
0x40038008 UART0_INTEN Interrupt Enable/Disable Controls
0x4003800C UART0_INTFL Interrupt Flags
0x40038010 UART0_BAUD_INT Baud Rate Setting (Integer Portion)
0x40038014 UART0_BAUD_DIV_128 Baud Rate Setting (Div 128 Decimal Portion)
0x40038018 UART0_TX_FIFO_OUT TX FIFO Output End (read-only)
0x4003801C UART0_HW_FLOW_CTRL Hardware Flow Control Register
0x40038020 UART0_TX_RX_FIFO Write to load TX FIFO, Read to unload RX FIFO
Rev.1.3 April 2015 Maxim Integrated Page 285