Maxim Integrated MAX32600, User Manual

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MAX32600 User’s Guide Pulse Train Engine 9.4 Enabling and Disabling Pulse Train Outputs
pulse_train_clk_scale (4-bit value) PT Peripheral Clock Rate (PTE
PCLK
)
5 1.5MHz
6 750kHz
7 375kHz
8 187.5kHz
9 93.75kHz
10-15 24MHz
9.4 Enabling and Disabling Pulse Train Outputs
9.4.1 Master Enable/Disable
The Pulse Train Engine supports the ability to start all configured and stop all active pulse trains simultaneously. This enables master control of all pulse train outputs
by firmware.
To disable all active pulse trains set the PTG_CTRL.enable_all to 0. Setting this bit to 1 will start all configured pulse trains simultaneously.
9.4.2 Enabling and Disabling Individual Pulse Train Outputs
For each individual pulse train output, writing a 0 to the PTn_RATE_LENGTH.mode register disables the specific pulse train output. Details for enabling specific
pulse train modes are described below .
9.5 Pulse Train Engine Modes
9.5.1 Pulse Train Mode
In Pulse Train mode, the engine supports lengths between 2- and 32-bits as set in the PTn_RATE_LENGTH.mode register. After setting the length, the PTn_TRAIN
register defines the sequence of 1s and 0s that will be shifted out (LSB first). To define the rate at which the data will be shifted out, the PTn_RATE_LENGT
−
H.rate_control register is written with a value representing the number of Peripheral Clocks between each bit of data sent. When the pulse sequence defined in the
PTn_TRAIN register has been completely sent out, the process repeats.
Note Setting the PTn_RATE_LENGTH.mode to 1 results in enabling Square Wave Mode .
Rev.1.3 April 2015 Maxim Integrated Page 490