MAX32600 User’s Guide
Peripheral Management Unit (PMU)
6
Peripheral Management Unit (PMU)
6.1
Overview
The Peripheral Management Unit (PMU) on the
MAX32600
is a DMA-based linked list processing engine. The PMU can perform operations and data transfers
involving memory and/or peripherals in the Advanced Peripheral Bus (APB) and Advanced High-performance Bus (AHB) peripheral memory space while the main
CPU is in a sleep state. This allows low-overhead peripheral operations — for which intensive CPU resources are not required — to be performed without the CPU,
significantly reducing overall power consumption. Additionally, for certain analog and digital operations, switching the CPU off and handling the operations using the
PMU provides a lower-noise environment that is critical for obtaining optimum analog-to-digital converter (
) and digital-to-analog converter (
) performance.
Key features of the PMU engine include:
• Six independent channels with round-robin scheduling to allow multiple parallel operations without requiring use of the CPU
• Suited for moving data to/from memory and peripherals
• Co-processor-like state machine within the
MAX32600
• Integrated AHB bus master
• Programmed using SRAM-based PMU op codes
• Interrupt conditions from peripherals to initiate PMU actions without requiring actual CPU-based interrupt handling
• Trigger interrupts to the CPU if needed
• Operation with Cortex M3 core in sleep state reduces power consumption
Rev.1.3 April 2015
Maxim Integrated
Page 193
