402-00005-00
Theory of Operation
2–20
Rev 02; February 8, 2002
2.6 TIMING AND SYNCHRONIZATION
The PCVisionplus has three major timing modes: PLL (Phase-Locked Loop), Internal timing (XTAL), or Variable
Scan (Vscan). There are two PLL modes; stripping sync from composite video, or locking to separate horizontal and
vertical sync inputs.
2.6.1 Sync Stripper PLL Mode
The first PLL mode uses the sync stripper to separate sync information from the video input. The PLL and PWG use
the stripped sync to generated clocking and timing. The PLL is programmed based on the timing requirements of the
incoming video. The PLL receives the stripped horizontal sync and outputs a clock PLLCLK, which is line-locked to
the incoming video and is used to digitize video and generate frame timing. The PTG is not used in PLL modes. The
PWG is programmed to frame the video.
Composite Video
ADC
Sync
Stripper
PLL
PWG
V
H
FIELD
PLL Clock
Memory Load
H
V
Selected
SYNC
F
separate composite sync
Timing
Figure 2–20. PLL Mode with Composite Sync
As shown in Figure 2–20, the PLL compares the stripped horizontal sync to the internal feedback, and generates the
PLL clock. The ADC uses the PLL clock to digitize the video input. Program the PWG for the desired video frame;
full frame or AOI. The PWG uses the PLL clock and the stripped horizontal, vertical, and field signals to frame the
video output.
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