402-00005-00
Index
Index–12
Rev 02; February 8, 2002
VBEVENINTSTAT, vertical blank even field interrupt status, 3–50
VBLANKINTEN, vertical blank interrupt enable, 3–52
VBLANKINTSTAT, vertical blank interrupt status, 3–50
VBODDINTEN, vertical blank odd field interrupt enable, 3–52
VBODDINTSTAT, vertical blank odd field interrupt status, 3–50
VCLKPOL, variable scan clock input polarity, 3–46
VCO
add 1 cycle, ADD, PLL, 4–10
remove 1 cycle, SWLW, PLL, 4–10
VCO gain, 4–8
VCO*, select source, INTVCO, 4–9
VERROR, vertical error status, 3–31
vertical
active size, VACT, 3–36
error status, VERROR, 3–31
gate start, VGSTRT, 3–31
offset, VOFF, 3–35
PWG timing, 2–32
sync end, VSEND, 3–30
sync output enable, VSYNCEN, 3–47
sync polarity, VSYNCPOL, 3–30
sync total, VTOTAL, 3–29
VGEND, vertical gate end register, 3–32
VGSTRT, vertical gate start, 3–31
VID, vendor ID register, 3–6
video input
field status, AMFLDSTAT, 3–67
specification, 1–2
vertical blank status, AMVBSTAT, 3–66
video inputs (AM control), mapping, BADR2, 3–13
VIDEOINSEL, video input select, 3–45
VOFF, vertical offset, 3–35
voltage reference, ADC, 2–17
VSCAN
clock input select, VSCLKSEL, 3–46
variable scan mode, 2–23
VSCLKSEL, VSCAN clock input select, 3–46
VSCSNTST, test mode enable, 3–48
VSEND, vertical sync end, 3–30
Vsync, output frame reset on Vsync output, FRSTONV, 3–42
VSYNCEN, vertical sync output enable, 3–47
VSYNCPOL, vertical sync polarity, 3–30
VTOTAL, vertical sync total, 3–29
W
WENMD, WEN Mode, 3–40
window generator, PWG, 2–29
X
XCNT, transfer count OCT, 3–80
XROM, expansion ROM address, (not supported), 3–15
XTAL, timing control, see PLL, 2–26
XTAL mode
programming example, 4–18
PWG operation, 2–31
synchronization, 2–22
XTALMDHPOL, crystal mode horizontal sync polarity, 3–28
Z
zoom, 2–8
BMZOOM, bus master zoom, 3–69
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