Coreco PCVisionplus, Hardware Reference Manual

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Introduction PCVisionplus

Hardware Reference
1–3 Rev 02; February 8, 2002
•
CLK, Pixel Clock Input: single-ended TTL, programmable polarity, Frequency 10 KHz to 53 MHz.
•
LEN, Line Enable Input: single-ended TTL, programmable polarity. Minimum de-asserted or inactive (reset)
pulse duration is one CLK period.
•
FEN, Frame Enable Input: single-ended TTL, programmable polarity. minimum de-asserted or inactive (reset)
pulse duration is one CLK period.
The sync stripper can be used in variable scan mode to strip field information from a composite sync signal, if avail-
able.
Table 1–1. Variable Scan Timing Parameters
Parameter Definition Minimum Maximum
/FENmin Minimum FEN inactive 1 CLK cycle
/LENmin Minimum LEN inactive 1 CLK cycle
Vp CLK period 18.86 ns 100 ns
Vh CLK high 9.43 ns 50 ns
Vl CLK low 9.43 ns 50 ns
Tsu LEN, FEN set–up to CLK rising edge 10 ns
Th LEN, FEN hold time from CLK rising edge 10 ns
Tsu LEN, FEN set–up to CLK falling edge (clock inverted) 10 ns
Th LEN, FEN hold time from CLK falling edge (clock inverted) 10 ns
CLK
/FEN
FEN
min
/LEN
min
LEN
Figure 1–1. Line and Frame Timing
T su
V p
V l V h
T h
CLK
LEN, FEN
Figure 1–2. Set Up and Hold Timing
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