DAC and PLL Programming
PCVisionplus
Hardware Reference
4–9
Rev 02; February 8, 2002
4.2.8.2 Phase Frequency Detector Gain (PFD) R/W
These bits control the PLL Phase Frequency Detector Gain. The default setting is 3. Always program these bits to 3
or 111 B.
PFD
PFD Gain
Fine Phase Adjust
0
0.2344uA/2
π
rad
3ns/V
1
0.9375uA/2
π
rad
3ns/V
2
3.750uA/2
π
rad
3ns/V
3
15.00uA/2
π
rad
3ns/V always use this value
4
1.875uA/2
π
rad
6ns/V
5
7.500uA/2
π
rad
6ns/V
6
30.00uA/2
π
rad
1.5ns/V
7
120.0uA/2
π
rad
.375ns/V
4.2.8.3 Phase Frequency Detector Enable (PDEN) R/W
This bit enables the PLL phase frequency detector. The default setting is 1 (enabled). Always program to 1.
PDEN
Function
0
PFD disabled not supported
1
PFD enabled
4.2.8.4 Loop Filter Select (INTFLT) R/W
This bit selects between external and internal loop filter mode. The PCVisionplus uses an external loop filter. This bit
should always be 0. Power-up default setting is 1, which must be changed to 0.
INTFLT
Function
0
External Loop Filter always
1
Internal Loop Filter not supported
4.2.8.5 VCO Select (INTVCO) R/W
This bit selects between internal and external VCO operation of the PLL. Set to internal VCO for proper operation.
Power-up default setting is 1.
INTVCO
Function
0
External VCO not supported
1
Internal VCO always
4.2.8.6 Feedback Divider Clock Select (CLKSEL) R/W
This bit selects the input clock to the feedback divider. PCVisionplus uses OUT1 feedback for PLL mode and VCO
feedback for XTAL mode. Power-up default setting is 0.
CLKSEL
Function
0
Not supported
1
OUT1 clock feeds Feedback divider always
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