402-00005-00
Index
Index–8
Rev 02; February 8, 2002
PLLA2, PLL register 2, 4–7
PLLA4, PLL register 4, 4–8
PLLA5, PLL register 5, 4–10
PLLA6, PLL register 6, 4–12
PLLA7, PLL register 7, 4–13
PLLCS, PLL chip select, 3–44
PLLPRG, PLL programming port register, 3–56
PLLREG3, PLL register 3, 4–7
PLLSDATA, PLL serial data, 3–56
polarity
field input, FLDPOL, 3–47
frame reset, FRSTPOL, 3–42
horizontal sync, HSYNCPOL, 3–28
input data strobe, INSTB_POL, parallel port, 3–59
input port interrupt, INPORT_IPOL, 3–59
line enable, LENPOL, 3–46
PLL feedback, FBKSEL, 4–10
PLL reference, REFPOL, 4–7
strobe, STRBPOL, 3–40
trigger, TRIGPOL, 3–39
variable scan clock input, VCLKPOL, 3–46
vertical sync, VSYNCPOL, 3–30
XTALMDHPOL, horizontla sync into PWG, 3–28
PORTCON, port control register , 3–58
power
specification, 1–7
to camera, 1–7
PREF, positive ADC reference, 2–17
PREVFLDSTART, previous field start status, 3–66
programmable
timebase, PTG, 2–27
window generator, PWG, 2–29
programmable clamp, 2–16
programming
LUT addressing, 3–61
PLL mode example, 4–14
serial DACs, 4–1
XTAL mode example, 4–18
PTG, programmable timebase generator, 2–27
PTGH1, PTG horizontal timing register, 3–27
PTGV1, PTG vertical timing register, 3–29
PTGV2, PTG vertical timing register, 3–31
PWG
in PLL mode, 2–29
programmable window generator, 2–29
variable scan mode, 2–31
XTAL mode, 2–31
PWG vertical timing, 2–32
PWGH, PWG horizontal timing register, 3–33
PWGV, PWG vertical timing register, 3–35
R
RDIV, PLL reference divider, 4–7
received
master abort, RMABT, 3–10
target abort, RTABT, 3–10
reference
DACs, 4–1, 4–2
divider, PLL, RDIV, 4–7
polarity, PLL, REFPOL, 4–7
reference voltage, ADC, 2–17
reference voltages, ADC, 2–16
REFPOL, PLL reference polarity, 4–7
register
ACQADR, acquire address status, 3–78
ACQREG, acquisition control, 3–64
acquire line address, ACQLINESTRT, 3–73
ALPHA, 3–61
AMINTCLR, AM interrupt status, 3–49
AMINTEN, AM interrupt control, 3–51
BADR0, base address zero, interface registers base, 3–12
BADR1, base address one, board ID registers, 3–13
BADR2, base address two, AM control registers, 3–13
BADR3, base address three, frame buffer control, 3–14
BADR4, base address three, image memory base, 3–14
BADR5, base address five, (not used), 3–15
BIST, built–in self test, 3–12
BMCS, bus master host control/status, 3–21
BMDST, bus master destination address status, 3–18
BMXC, bus master transfer count status, 3–18
BRDSTAT, board status, 3–23
CACPROG, DAC programming data port, 3–56
CALN, cache line size, 3–11
CLCD, class code, 3–11
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