402-00005-00
Theory of Operation
2–16
Rev 02; February 8, 2002
The different signal response of the two low-pass filters creates a difference in the signal delay, of approximately 35
ns, between the two filter paths. This difference must be compensated for when switching between the low-pass
filters. At a sample rate of 20 ns (50 MHz) the shift is approximately 0 to 1 pixel, worst case. At a sample rate of 60 ns
(16.7 MHz) the shift is approximately 1 to 2 pixels, worst case. You may see a visible horizontal shift in the image
when you select between the two low-pass filters. You can choose to ignore this shift, or you can adjust the values of
HOFF and HACT, moving the video window 1 or 2 pixels right or left as needed, to realign the image.
2.5.4 DC Restoration
The video input is AC coupled. DC restoration is required to clamp the “back porch” of the video signal to the ap-
propriate voltage level for digitization. The back porch is the reference “black level” voltage in analog video signals,
and must be used by the ADC as a black reference. Two modes of generating a clamp pulse are provided; Sync Strip-
per Clamp and Programmable Clamp. Both use the programmable clamping voltage.
2.5.4.1 Sync Stripper Clamp Pulse
The sync stripper receives the composite video signal, and produces separate horizontal, vertical, composite, and
field signals, as well as a clamp pulse positioned on the back porch of the incoming video signal. When the stripped
clamp pulse is selected, the DC restore circuit clamps the back porch as illustrated in Figure 2–16. Sync Stripper
clamping can only be used with standard RS170 and CCIR video signals.
Composite Video
Sync Stripper Sample Pulse
HSYNC
Back Porch
Clamp
Pulse
Figure 2–16. DC Restore with Sync Stripper Sample Pulse
In Figure 2–16 the clamp circuit samples the back porch voltage level of the AC-coupled video signal for every line,
and adjusts (clamps) the back porch of the video signals to match a programmable clamp voltage in the Clamp Volt-
age DAC. The ADC uses this voltage level as the internal reference for black. The optimum setting for the clamp
voltage is equal to the negative reference voltage (NREF) of the ADC (plus a small correction factor).
2.5.4.2 Programmable Clamp Pulse
A programmable clamp pulse is available, and gives better response than the Sync Stripper clamp. The program-
mable clamp pulse is referenced to horizontal sync input or PTG sync, and can be positioned by programming the
beginning and end counts. The counters are clocked by the internal crystal clock in the PLL circuit, and are indepen-
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