Coreco PCVisionplus, Hardware Reference Manual

Page: 157 / 206

402-00005-00 DAC and PLL Programming
4–6 Rev 02; February 8, 2002
4.2.4 PLL Register 0 (PLLA0)
0 7
PLL Address 0x0
FDIV7 FDIV6 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
8 15
Reserved Reserved Reserved Reserved Reserved FDIV10 FDIV9 FDIV8
PCR_PLLA0_16
Bit Mnemonic Function
10–0 FDIV FeedBack Divider
15–11 Reserved Don’t care
4.2.4.1 FeedBack Divider (FDIV) R/W
The eleven FDIV bits control the PLL feedback divider which divides the VCO by the set Modulus. The Modulus =
FDIV + 1. The minimum setting is 64 and the maximum is 2048. Default FDIV setting at power up is 0x04F (79) so
the default Modulus = 80 at power-up. Refer to the Examples for programming PLL and XTAL mode, for calculating
PLL register values.
4.2.5 PLL Register 1 (PLLA1)
0 7
PLL Address 0x1
LO7 LO6 LO5 LO4 LO3 LO2 LO1 LO0
8 15
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PCR_PLLA1_16
Bit Mnemonic Function
7–0 LO Feedback Sync Pulse Low
15–8 Reserved Don’t care
4.2.5.1 Feedback Sync Pulse Low (LO) R/W
These bits program an additional PLL feedback divider output with a programmable phase, which can be selected at
Output 3. The default setting is 0x3. PCVisionplus does not use this mode of the PLL, and this register should always
be programmed to 0x0.
4.2.6 PLL Register 2 (PLLA2)
0 7
PLL Address 0x2
HI7 HI6 HI5 HI4 HI3 HI2 HI1 HI0
8 15
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PCR_PLLA2_16
Bit Mnemonic Function
7–0 HI Feedback Sync Pulse High
15–8 Reserved Don’t care
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