402-00005-00
Theory of Operation
2–28
Rev 02; February 8, 2002
The PTG must be programmed to match the camera in use. The PTG has a vertical and horizontal counter and several
registers to determine the size of the sync pulses in pixel clocks or lines.
The horizontal sync is derived from two register settings HTOTAL and HESYNC. The HTOTAL value determines
the number of pixel clocks in half of a horizontal sync line (up to 1024 clocks). The HTOTAL value is loaded into a
counter which counts off the number of pixel clocks programmed. At the end of the count, the PTG outputs a low
going Hsync pulse (polarity output to camera is programmable) and restarts the count. The sync pulse stays low the
number of pixel clocks programmed in HESYNC (up to 256 clocks). Internal to the PTG, Hsync is formulated from
HTOTAL and HESYNC as follows:
Total Hsync Time = HTOTAL x 2
and
Total Hsync low time = HESYNC
Because Hsync is derived from two times the horizontal register setting, the Hsync time is always on even pixel clock
boundaries (increasing HTOTAL by 1 actually increases Hsync by two pixel clocks).
PTG Internal Hsync
HTOTAL
Hsync Low Time
PTG Hsync Output
Figure 2–27. Timing Generator Horizontal Sync Output
In Figure 2–27, HESYNC determines when the PTG Horizontal Sync goes high, based on the horizontal counter.
The PTG Horizontal Sync output is twice HTOTAL. This means the actual pixel resolution of sync output is two
pixel clocks.
The maximum Hsync low time is 256 pixels and maximum Hsync high time is (2048 – Hsync low) pixels.
The PTG vertical sync is generated in a similar fashion by two values that determine the total number of half lines in a
field/frame time and the number of half lines in the Vsync low period. VTOTAL sets the number of half lines and
VSEND sets the Vsync low time. The PTG can generate both interlaced and non-interlaced frame timing based on
the number of half lines programmed in the VTOTAL register. If VTOTAL is ODD (lsb=1) then frame timing is
interlaced, if EVEN (lsb=0) then frame timing is non-interlaced.
The Maximum settings of the programmable timing generator are:
PTG max = 2K horizontal x 2K vertical, (2048 by 2048)
The active time for the programmable timing generator is:
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