402-00005-00
Index
Index–6
Rev 02; February 8, 2002
AMINTEN, AM interrupt, 3–78
BMINTEN, bus master complete interrupt, 3–77
PCI bus, INTEN, 3–19
interrupts, PCI–bus, 2–3
INTFLT, PLL loop filter select, 4–9
INTLN, interrupt line, 3–15
INTPIN, interrupt pin, 3–16
INTST, PCI interrupt status, 3–20
INTSTAT, interrupt status register, 3–75
INTVCO, VCO select, 4–9
IOEN, I/O space access enable, 3–7
L
LAT, latency timer, 3–11
latch, trigger mode select, TRIGMD, 3–43
latched, data input, INREG_ENB, 3–58
latency, bus master transfers, 2–13
latency timer, LAT, 3–11
LCOUNT, PLL load counter, 4–12
LDLG, PLL fine phase adjust lead/lag, 4–11
LENPOL, line enable polarity, 3–46
line enable, polarity, LENPOL, 3–46
line rate, DAC, 4–3
line size, cache, CALN, 3–11
line time, total, HTOTAL, 3–27
LO, feedback sync pulse low, PLL, 4–6
load counter, PLL, LCOUNT, 4–12
loop filter, select, INTFLT, 4–9
low–pass filter, 2–15
LPFSEL, low–pass filter select, 3–45
LSBMASK, interrupt address lsb mask, 3–74
LUT
high WORD access, 3–61
look–up tables, 2–18
low WORD access, 3–61
static address, ILUTSADR, 3–48
LUT programming, 3–61
M
MAINT, master abort interrupt status, 3–20
mapping
AM control registers, BADR2, 3–13
board ID registers, BADR1, 3–13
frame buffer control registers, BADR3, 3–14
image memory, BADR4, 3–14
interface control registers, BADR0, 3–12
master abort, recieved, RMABT, 3–10
MAXLAT, maximum latency, 3–16
MBOX, mail box registers, 3–17
MEMEN, memory space access enable, 3–7
MEMINIT, memory initialization register, 3–71
memory
host access, 2–1, 2–5
mapping, BADR4, 3–14
specification, 1–5
MINGNT, minimum grant, 3–16
miscellaneous input status, MISCIN, 3–48
miscellaneous output, control, MISCOUT, 3–48
MISCIN0, misc input status, 3–48
MISCOUT, control, output control, 3–48
multiple image acquire, 2–6
N
NEWAQ, new acquire command status, 3–66
NOCLAMP, no clamp region, 3–55
normal, acquisition, 2–5
NREF, negative ADC reference, 2–17
O
OCT
output control table, 2–8
specification, 1–5
transfer count, XCNT, 3–80
OCTDATA, output control table data register, 3–79
OCTSTART, OCT start address register, 3–75
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