PCVisionplus
Hardware Reference
Theory of Operation
2–27
Rev 02; February 8, 2002
source (either stripped Hsync or separate Hsync) for phase alignment. Any detected phase difference generates an
error voltage which modifies the VCO clock to correct for the difference. The VCO clock is passed to the output post
scalar and the load counter to divide the high frequency VCO clock down to the desired PLL clock rate.
PLLSRC
Stripped HSYNC
Separate HSYNC
Crystal Oscillator
Reference
PLL
EXTPOL
Phase
Frequency
Detector
VCO
230 MHz
Max Freq
Feedback
Divider
Output
Post Scaler
Load
Counter
1/4
OMUX1
Clock Output
Divider
1/R
REF
MUX
14.318 MHz
PLL Clock
or
XTAL Clock
Figure 2–26. PLL and Clock Synthesizer
The VCO is optimized to run at a maximum frequency of 230 MHz. When programming the Output Post Scalar,
Load Counter, and the feedback path, the goal is to achieve the highest VCO frequency without going over 230 MHz.
In PLL mode, the same Hsync source input to the PLL also drives the PWG. The example that follows gives the
details of how to program the PLL registers to achieve a desired clock rate.
For XTAL mode operation, the 14.318 MHz reference oscillator is selected, and the feedback path is also driven with
the PLL clock output. The incoming reference frequency is divided by in the reference divider, and input to the phase
detector. The feedback path is programmed to divide the PLL output clock down to match the divided reference
oscillator frequency. The phase detector then checks the two signals for phase alignment and adjusts the VCO as
needed. The VCO output is passed to the Output Post Scalar and the Load Counter which divide down the VCO clock
to the required pixel clock rate. When programming the VCO, feedback path, and output path; the goal is to achieve
maximum VCO operating frequency of 230 MHz. The PTG uses the XTAL clock to generate the Hsync and Vsync
driven to the camera and to the PWG for video framing. The ADC uses this same XTAL clock for video sampling.
2.7.4 Programmable Time Base Generator (PTG)
The PTG is used in internal timebase (XTAL) mode to generate horizontal and vertical sync for gen-locking camer-
as. The PTG uses a clock derived from a reference oscillator and the PCVisionplus frequency synthesizer to generate
horizontal and vertical sync and Vertical reset (VRESET) to output to a camera. The PTG horizontal and vertical
syncs are output to CAM0 and CAM1.
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