Registers
PCVisionplus
Hardware Reference
3–7
Rev 02; February 8, 2002
3.1.3 PCI Command (PCICMD) R/W
0
7
Address offset 0x4
0
PAREN
0
0
0
PCIBMEN
MEMEN
IOEN
8
15
0
0
0
0
0
0
FBB
SREN
PCICMD
This register provides coarse control over the PCVisionplus ability to generate and respond to PCI-bus cycles. Indi-
vidual bits are available to enable and disable the PCI interface. All bits shown as zero are reserved and read only.
This register is initialized with the assertion of the PCI #RESET line.
Bit
Mnemonic
Function
0
IOEN
I/O Space Access Enable
1
MEMEN
Memory Space Access Enable
2
PCIBMEN
Bus Master Enable
3–5
Reserved
Must be zero
6
PAREN
Parrity Error Enable
7
Reserved
Must be zero
8
SEREN
System Error Enable
9
FBB
Fast Back-to-back Transfer Enable
10–15
Reserved
Must be zero
3.1.3.1 I/O Space Enable (IOEN) R/W
This bit allows the PCVisionplus to decode and respond as a target to I/O cycles which are to regions defined as I/O
space in the base address registers. This bit is initialized to zero at power-up. This bit should be written to one as part
of the initialization routine.
IOEN
Function
0
Disable I/O access
1
Enable I/O access
3.1.3.2 Memory Space Enable (MEMEN) R/W
This bit allows the PCVisionplus to decode and respond as a target to memory cycles which are to regions defined as
memory space in the base address registers. This bit is initialized to zero at power-up. This bit should be written to
one as part of the initialization routine.
MEMEN
Function
0
Disable memory access
1
Enable memory access
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