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402-00005-00

Registers

3–8

Rev 02; February 8, 2002

3.1.3.3 Bus Master Enable (PCIBMEN) R/W

This bit allows the PCVisionplus to function as a bus master in the PCI system. This bit is initialized to zero at power-
up. This bit should be written to one as part of the initialization routine.

PCIBMEN Function

0

Disable bus master mode

1

Enable bus master mode

3.1.3.4 Parity Error Enable (PAREN) R/W

This bit allows the PCVisionplus to check for parity errors and generate the PCI signal #PERR when an error is de-
tected. This bit is initialized to zero at power-up.

PAREN

Function

0

Disable parity detection

1

Enable parity detection

3.1.3.5 System Error Enable (SEREN) R/W

This bit allows the PCVisionplus to drive the #SERR pin upon detection of a system error. #SERR driven usually
indicates a parity error on the PCI address and control bus. This bit is initialized to zero at power-up.

SEREN

Function

0

Disable system error

1

Enable system error

3.1.3.6 Fast Back-to-Back Transfer Enable (FBB) R/W

This bit allows the PCVisionplus to perform fast back-to-back bus master cycles. This bit is initialized to zero at
power-up.

FBB

Function

0

Disable fast back-to-back transfer

1

Enable fast back-to-back transfer

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Summary of Contents for PCVisionplus

Page 1: ...ized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Re...

Page 2: ...Coreco Imaging Inc PCVisionplus Hardware Reference Manual 402 00005 00 Revision 02 February 8 2002 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 3: ...ept with the express written consent of Coreco Imaging Inc The information in this document is subject to change without notice Coreco Imaging Inc makes no representations or warranties with respect t...

Page 4: ...ers provides detailed descriptions of every register and bit that controls the PCVisionplus Chapter 4 DAC and PLL Programming provides detailed descriptions of the serial interfaces and program ming e...

Page 5: ...t bit The use of lower case letters means bits LSB MSB Least significant byte most significant byte The use of capitals letters means bytes DWORD A 32 bit address or data value WORD A 16 bit address o...

Page 6: ...2 12 Environmental 1 7 1 2 13 Camera Power 1 7 Chapter 2 Theory of Operation 2 1 Overview 2 1 2 2 Host Interface 2 1 2 2 1 Memory Access 2 1 2 2 2 Register Access 2 2 2 2 2 1 PCI Configuration Regist...

Page 7: ...ammable Clamp Pulse 2 16 2 5 5 Programmable Clamp Voltage DAC 2 17 2 5 6 Analog to Digital Converter 2 17 2 5 7 Programmable References 2 17 2 5 8 Input LUT 2 18 2 6 Timing and Synchronization 2 20 2...

Page 8: ...3 1 3 5 System Error Enable SEREN R W 3 8 3 1 3 6 Fast Back to Back Transfer Enable FBB R W 3 8 3 1 4 PCI Status PCISTAT R W1C 3 9 3 1 4 1 Data Parity Reported DTPAR R W1C 3 9 3 1 4 2 Signaled Target...

Page 9: ...t Interrupt Status MAINT R W1C 3 20 3 2 4 6 Target Abort Interrupt Status TAINT R W1C 3 20 3 2 5 Bus Master Host Control Status BMCTL R W 3 21 3 2 5 1 FIFO Full FIFOFL R O 3 21 3 2 5 2 FIFO 4 Plus FIF...

Page 10: ...R O 3 36 3 4 5 4 TTL Trigger 1 Status EXTRIGSTAT1 R O 3 36 3 4 5 5 15 Pin TTL Trigger 0 Status EXTRIGSTAT0_15 R O 3 37 3 4 5 6 Opto Isolator Trigger 0 Status OPTOSTAT0 R O 3 37 3 4 5 7 Opto Isolator...

Page 11: ...Test Mode VSCANTST R W 3 48 3 4 7 17 Misc Output MISCOUT2 MISCOUT1 MISCOUT0 R W 3 48 3 4 7 18 Misc Input MISCIN2 MISCIN1 MISCIN0 R O 3 48 3 4 7 19 Input LUT Static Address ILUTSADR R W 3 48 3 4 8 AM...

Page 12: ...8 3 4 15 3 Input Port Strobe Polarity INSTRBPOL R W 3 59 3 4 15 4 Input Buffer Clear INREGCLR R W 3 59 3 4 15 5 Input Port Interrupt Polarity IPINTPOL R W 3 59 3 4 15 6 Input Port Interrupt Input Stat...

Page 13: ...errupt Status ACQLINEINTSTAT R W1C 3 76 3 5 8 2 Bus Master Complete Interrupt Status BMINTSTAT R W1C 3 76 3 5 8 3 AM Interrupt Status AMINTSTAT R W1C 3 76 3 5 8 4 End of Frame Interrupt Status EOFINTS...

Page 14: ...4 2 8 2 Phase Frequency Detector Gain PFD R W 4 9 4 2 8 3 Phase Frequency Detector Enable PDEN R W 4 9 4 2 8 4 Loop Filter Select INTFLT R W 4 9 4 2 8 5 VCO Select INTVCO R W 4 9 4 2 8 6 Feedback Div...

Page 15: ...4 17 4 4 Programming Example for XTAL Mode 4 18 4 4 1 Notes on Programming XTAL Mode 4 22 4 5 Tables for Programming Examples 4 24 Appendix A Connectors and Cables Connectors A 1 15 Pin D Sub A 2 26...

Page 16: ...Stage 2 14 Figure 2 14 Input Voltage 2 15 Figure 2 15 Low pass Filtering 2 15 Figure 2 16 DC Restore with Sync Stripper Sample Pulse 2 16 Figure 2 17 DC Restore with Programmable Clamp Pulse 2 17 Fig...

Page 17: ...Mode 3 62 Figure 3 11 Input LUT Oversample Mode 3 62 Figure 3 12 Frame Buffer Control Register Map 3 63 Figure 3 13 Bus Master Data Shift 3 69 Figure 3 14 Add On Register Map 3 82 Figure 4 1 PLL Seri...

Page 18: ...eak out Cables for PCVisionplus A 5 Table A 5 Breakout Cable 509 00066 00 Pin out A 6 Table A 6 Miscellaneous Cable 509 00065 00 Pin out A 8 Table A 7 BCBL PCV1 Pin out A 8 Table A 8 BCBL PCV2 Pin out...

Page 19: ...402 00005 00 Preface xviii Rev 02 February 8 2002 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 20: ...is available for processing or other system resources 1 1 PCI INTERFACE The PCI bus interface allows the PCVisionplus to operate as both PCI bus master and target slave Only DWORD 32 bit access is sup...

Page 21: ...tion automatic clamp pulse from stripped sync or programmable clamp pulse programmable clamp voltage 0 to 2 5 Volts Low Pass Filters 6 5 MHz and 12 5 MHz Input gain 2 1 fixed Programmable ADC positive...

Page 22: ...composite sync signal if avail able Table 1 1 Variable Scan Timing Parameters Parameter Definition Minimum Maximum FENmin Minimum FEN inactive 1 CLK cycle LENmin Minimum LEN inactive 1 CLK cycle Vp C...

Page 23: ...h min 2 V Minimum high level voltage Vl max 0 5 V Maximum low level voltage Ii max 1 uA Maximum input current H 0 4 1 6 V Minimum Maximum hysteresis R 10 kohms PCVisionplus pull up resistors 250 ns Mi...

Page 24: ..._OUT Vh min 2 4 V Minimum high level output voltage Vl max 0 55 V Maximum low level output voltage Ih max 15 mA Maximum high level output current Il max 64 mA Maximum low level output current 1 2 6 Im...

Page 25: ...lors Optional padding 8 bit data to 16 bit during bus master transfer to VGA secondary surface for 4 2 2 display 16 bit secondary surface 1 2 11 Parallel I O Port One parallel I O port 8 bit TTL input...

Page 26: ...Hi Lo Hi Lo Power up all ones Power up all zeros Expansion Slot Connectors Figure 1 4 PCVisionplus Connectors and Jumper 1 2 12 Environmental Board Size PCI short card 6 88 by 4 205 inches 17 73 by 1...

Page 27: ...402 00005 00 Introduction 1 8 Rev 02 February 8 2002 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 28: ...ource Only Bus Master write PCVisionplus writing data to the PCI bus is supported As a target the PCVisionplus can be accessed by other Bus Masters in the host system The PCVisionplus supports read an...

Page 29: ...ntrol over the board operation All five sets of registers must be properly initialized for operation of PCVisionplus 2 2 2 1 PCI Configuration Registers The PCI Configuration Registers are required fo...

Page 30: ...BADR2 register The input LUT is mapped with these registers 2 2 2 5 Frame Buffer Control Registers The Frame Buffer Control Registers control image memory frames interrupts image acquisition scatter...

Page 31: ...vertical blank even odd or any and end of frame are all sources available to generate PCI bus interrupts The INTLN register and the INTEN bit of the INTCTL_32 register must both be set properly for a...

Page 32: ...g External Trigger acquisitions are based on external trigger signals and camera timing 2 3 1 1 Normal Acquisition The beginning and ending of a normal acquisition is based on the framing signal FEN f...

Page 33: ...quire bits Data Grab status snap requested odd even odd even odd external trigger valid data Figure 2 4 Triggered Acquire 2 3 1 3 Multiple Frame Acquire Mode PCVisionplus has the ability to acquire an...

Page 34: ...ame This sets up a ping pong acquire buffer which can be useful to maintain acquire and transfer rates 2 4 BUS MASTER OPERATION During a bus master operation the PCVisionplus is granted control of the...

Page 35: ...fers The OCT supports a variety of PCVisionplus features includ ing image re sequencing and ROI region of interest output 2 4 4 Output Formatting The memory control and bus master controller work toge...

Page 36: ...ws the first of two transfers for the zoom by 4 The transfer count must be multiplied by four in zoom by 4 The data output is four times the data read from the image memory Image Buffer Memory pixel1...

Page 37: ...Mode In 12 bit mode Decimate by 2 performs a shift and pack operation This is very useful for quickly displaying 8 bit data from un normalized 12 bit data without using host computer resources for sh...

Page 38: ...surface or a YCRCBMONO display sink on VGA boards that support the secondary surface also called streams processing Padding is a function of the bus master interface and does not affect pixels in PCV...

Page 39: ...11 12 bit Padding 2 4 4 4 Clipping The PCVisionplus provides an 8 bit data clipping feature that forces pixels with values between 0x0 and 0xF to the value 0x10 and forces pixels with values between 0...

Page 40: ...dent on the host system and the target s capabilities Bus traffic other bus masters arbitrating for and gaining bus ownership and target capabilities PCVisionplus can only transfer data as fast as the...

Page 41: ...video signals provides the correct gain needed for the desired 1 5 Vpp sampling window of the ADC Standard video signal ampli tude is 0 714 mV and 2 1 times 0 714 1 5 Volts To achieve best performance...

Page 42: ...ly 6 5 MHz Frequen cies above this can be eliminated using the low pass filters Sampling rates for standard video are 10 MHz up to 14 MHz If frequencies at or above the sampling rate are present they...

Page 43: ...ripper receives the composite video signal and produces separate horizontal vertical composite and field signals as well as a clamp pulse positioned on the back porch of the incoming video signal When...

Page 44: ...to match the negative reference voltage of the ADC The voltage swing of the DAC is 0 to 2 5 Volts The default DAC setting for 1 75 Volts is 0x1666 5734 decimal Desired Clamp Level 1 75 V DAC value des...

Page 45: ...sample Enable bit OVRSM controls the input LUT configuration which has a great affect on how the LUT is programmed The Input Data Format bit INMODE controls how data is read from the LUT output and pa...

Page 46: ...t oversampling the pixel data program the LUT to ignore the high byte input delayed pixel by repeating the same data pattern If you are oversampling program the LUT to average the values input on the...

Page 47: ...horizontal sync and outputs a clock PLLCLK which is line locked to the incoming video and is used to digitize video and generate frame timing The PTG is not used in PLL modes The PWG is programmed to...

Page 48: ...sync inputs is programmable allowing positive or negative polarity input active high or active low signals Separate HSYNC Input ADC PLL PWG V H PLL Clock Memory Load Timing Separate VSYNC Input non C...

Page 49: ...mmed to standard and non standard camera timing ADC Clock PTG PWG V H FIELD XTAL Memory Load Timing Synthesizer non Composite Video Clock XTAL Figure 2 22 Internal Timing Mode XTAL Mode Figure 2 22 il...

Page 50: ...programmable If the video is interlaced and sync information is available on the video signal composite sync on video the sync stripper can be used to extract the field information ADC PWG Memory Loa...

Page 51: ...s LEN line enable FEN frame enable CLK variable scan clock from CAM0 or CAM1 Only positive digital signals are supported in variable scan mode Negative signals and ana log timing are not supported The...

Page 52: ...er The sync stripper separates synchronization information from a composite video input on the video signal CAM0 or CAM1 The horizontal sync Hsync output of the sync stripper is used in the PLL where...

Page 53: ...ating the Sync Stripper DAC value is NB 1 7 line rate in KHz 45 KHz 0 000169 Where NB is the programmed 13 bit DAC value 35 6 KHz 66 5 KHz 56 2 KHz 49 5 KHz 25 3 KHz 15 KHz 4914 6 4095 5 3276 4 2457 3...

Page 54: ...ce oscillator is selected and the feedback path is also driven with the PLL clock output The incoming reference frequency is divided by in the reference divider and input to the phase detector The fee...

Page 55: ...tually increases Hsync by two pixel clocks PTG Internal Hsync HTOTAL Hsync Low Time PTG Hsync Output Figure 2 27 Timing Generator Horizontal Sync Output In Figure 2 27 HESYNC determines when the PTG H...

Page 56: ...ced video formats The PWG uses the incoming timing to start the internal horizontal and vertical counters The values HOFF HACT VOFF and VACT define the size of the Active video window loaded into memo...

Page 57: ...a no load region HACT is programmed to the total horizontal line time At the end of the HACT count end of active period the FIFO load is disabled and the horizontal counter resets and waits for the n...

Page 58: ...the appropriate regis ter settings HBLANK Video PTG HSYNC memory write enable valid video window H Active H Offset HOFF HACT Figure 2 30 PWG Horizontal Timing Internal Timing Mode In Figure 2 30 HACT...

Page 59: ...f the video is cropped 2 7 5 4 PWG Vertical Timing Two values determine the number of lines loaded into the FIFO per frame VACT holds the number of lines per frame including blanking The selected edge...

Page 60: ...2 line targeted to crop and the first line of the odd field which is valid data but is lost due to the nature of the interlaced video and how the PWG does cropping The same thing happens on the last...

Page 61: ...rigger mode The TRGISEL bits se lect external input or software trigger The TRIGPOL bit selects the rising or falling edge of the incoming external trigger pulse The correct trigger event software or...

Page 62: ...ot useable Video VBLANK Vsync Trigger Input memory write enable No strobe Region Figure 2 34 Coincident Strobe Effect Figure 2 34 shows the effect when the trigger occurs coincident with Vsync In this...

Page 63: ...progress This mode allows back to back cycles with strobes enabled as the new cycle will start immediately prior to Vsync which was shown to incur a field delay 2 7 7 4 Skip Field Mode A skip field m...

Page 64: ...ccurs coincident with VSYNC the strobe is delayed past the no strobe region and the acquire is delayed to the next field The strobe pulse is one line in duration and polarity is programmable In Figure...

Page 65: ...e frame is acquired the PWG again halts in vertical blank A frame reset pulse is output on the video connector coincident with the external trigger to asynchronously reset the camera The FRSTSZ bit se...

Page 66: ...NK HBLANK Trigger Input FRST 1 line FRST TRGEN0 Strobe TRGCYC0 PTG Vsync FROFF Froff mode STRBDLY FIFO Load Figure 2 37 Triggered Acquire in Frame Reset In Figure 2 37 the external trigger pulse immed...

Page 67: ...402 00005 00 Theory of Operation 2 40 Rev 02 February 8 2002 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 68: ...ntrol Registers Figure 3 3 shows the mapping of the Board ID Registers Figure 3 4 shows the mapping of the Acquisition Control Registers Figure 3 5 shows the mapping of the Frame Buffer Control Regist...

Page 69: ...Device ID DID PCI Command PCICMD PCI Status PCISTAT Revision ID RID Class Code CLCD Master Latency Timer LAT Header Type HDR Built in Self Test BIST Base Address 0 BADR0 Base Address 2 BADR2 0x1C 0x1...

Page 70: ...TL Bus Master Control Status BMCTL 0x8 Mailbox3 MBOX3 0x4 Mailbox 2 MBOX2 0x0 Mailbox 1 MBOX1 3 17 3 17 3 17 3 17 3 18 3 18 3 19 3 21 BADR0 Figure 3 2 PCI Interface Control Register Map Board ID Regis...

Page 71: ...LLPROG BADR2 3 53 3 53 3 56 3 56 3 57 Input Control 1 INCON1 0x18 3 38 Reserved PIO Output Port OUTPORT 0x3C 0x40 PIO Input Port INPORT 0x44 0x50 0x3FFFF AM Interrupt Status AMINTCLR 3 60 3 60 3 51 3...

Page 72: ...isition Start Address ACQSTRT 0x18 3 72 Reserved 0xC0010 0xFFFFF 3 71 3 81 3 73 0x14 Memory Initialization MEMINIT 0x0C Reserved 0x04 0x08 Reserved Reserved 0x00 Acquisition Control ACQREG 3 64 0x10 B...

Page 73: ...1 Vendor Identification VID R O 0 7 Address offset 0x0 0 0 1 0 1 1 1 1 8 15 0 0 0 1 0 0 0 1 VENDOR_ID This register contains the Imaging Technology Incorporated Coreco Imaging Inc vendor identificatio...

Page 74: ...r Enable 9 FBB Fast Back to back Transfer Enable 10 15 Reserved Must be zero 3 1 3 1 I O Space Enable IOEN R W This bit allows the PCVisionplus to decode and respond as a target to I O cycles which ar...

Page 75: ...at power up PAREN Function 0 Disable parity detection 1 Enable parity detection 3 1 3 5 System Error Enable SEREN R W This bit allows the PCVisionplus to drive the SERR pin upon detection of a system...

Page 76: ...ro 11 STABT Signaled Target Abort 12 RTABT Received Target Abort 13 RMABT Received Master Abort 14 SSERR Signaled System Error 15 DPARE Detected Parity Error 3 1 4 1 Data Parity Reported DTPAR R W1C T...

Page 77: ...doesn t respond This bit is cleared by writing it to one 1 RMABT Function 0 No master abort 1 Master abort occurred 3 1 4 5 Signaled System Error SSERR R W1C This bit is set whenever the PCVisionplus...

Page 78: ...ass code for the PCVisionplus as defined by PCI SIG The PCVisionplus is defined as a Multimedia Device Base Class 0x04 of type Video Sub Class 0x00 This register is boot loaded at power up and is read...

Page 79: ...DR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 8 15 ADR15 ADR14 ADR13 ADR12 ADR11 ADR10 ADR9 ADR8 BADR0 16 23 ADR23 ADR22 ADR21 ADR20 ADR19 ADR18 ADR17 ADR16 24 31 ADR31 ADR30 ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 T...

Page 80: ...The Board ID Register space is defined as 32 bit DWORD access only 3 1 13 Base Address Two BADR2 R O 0 7 Address offset 0x18 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 8 15 ADR15 ADR14 ADR13 ADR12 ADR11...

Page 81: ...the user application The Frame Buffer Control Register Address space is defined as 32 bit DWORD access only 3 1 15 Base Address Four BADR4 R O 0 7 Address offset 0x20 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR...

Page 82: ...xpansion ROM is not supported on the PCVisionplus This register is reserved and will return all zeros if read This register is read only 3 1 18 Interrupt Line INTLN R W 0 7 Address offset 0x3C INTLN7...

Page 83: ...sionplus will require for bus master write transfers The register is boot loaded at power up with a value of 0xFF 255 which indicates a desired minimum bus master access time of 64 microseconds 255 x...

Page 84: ...ses the fields in this set are used with the BMC In some cases the fields in this set are not used 3 2 1 Mailbox Registers MBOX1 MBOX2 MBOX3 MBOX4 R W 0 7 BADR0 0x0 0x4 0x8 0xC DATA7 DATA6 DATA5 DATA4...

Page 85: ...s will be zero during the address phase of a bus master write transfer indicating to the target that the data from the PCVisionplus is in linear format and that the PCVision plus is burst capable ther...

Page 86: ...a PCVisionplus interrupt defined in the INTENREG or AMINTEN registers Always program bits defined as zero or one to their respective values Bit Mnemonic Function 0 7 Reserved Must be zero 8 11 Reserve...

Page 87: ...he transfer The BINTEN bit must be one for this bit to operate This bit is always zero if the BINTEN is zero This bit operates as read write one clear Writing one to this bit resets it to zero Writing...

Page 88: ...e 9 23 Reserved Must be zero 24 RST Software Reset 25 31 Reserved Must be zero 3 2 5 1 FIFO Full FIFOFL R O This bit is set to one when the FIFO becomes full during a bus master transfer from the PCVi...

Page 89: ...om the PCVisionplus to the PCI bus completes Completion of a bus master cycle is when the value in the Bus Master Transfer Count register reaches zero This bit is read only BMDONE Function 0 Bus maste...

Page 90: ...d Status BRDSTAT R O 0 7 BADR1 0x00 REV1 REV0 CM PIOLSTAT FPGARDY FPGA BLD BLD 8 15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCP_BLDSTAT_32 16 23 Reserved Reserved Reser...

Page 91: ...oftware should ignore this bit FPGARDY Status 0 Byte load not complete 1 Byte load completed 3 3 1 4 PIO Level Jumper Setting PIOLSTAT R O This status bit indicates the setting of the jumper which def...

Page 92: ...m is reset Applications must never read or write to this address 3 3 3 FPGA Reset ORCARST W O 0 7 BADR1 0x08 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 8 15 Reserved Reser...

Page 93: ...30 0x34 Software Trigger SOFTTRIG DAC Programming Port DACPROG Timer Counter TIMER PLL Programming Port PLLPROG BADR2 3 53 3 53 3 56 3 56 3 57 Input Control 1 INCON1 0x18 3 38 Reserved PIO Output Port...

Page 94: ...ue is the number of pixel clocks in half the horizontal line time or sync time duty cycle including both sync high and sync low time In internal timing XTAL mode the PTG generates the horizontal sync...

Page 95: ...ync low 256 pixel clocks 3 4 1 3 Horizontal Sync Output Polarity HSYNCPOL R W The HSYNCPOL bit defines the polarity of the horizontal sync signal driven out onto the camera connectors in internal timi...

Page 96: ...care 3 4 2 1 Vertical Sync Total VTOTAL R W VTOTAL defines the Programmable Timing Generator PTG vertical sync time or total frame time The 12 bit val ue is the total number of half lines in the Vsyn...

Page 97: ...ty of the vertical sync signal in internal timing mode XTAL The Vsync output on the camera connector can be disabled by the VSYNCEN bit INCON2 register This bit is don t care in PLL modes VSYNCPOL Fun...

Page 98: ...ved Reserved Reserved Reserved Reserved Reserved Reserved The PTGV2 register defines the vertical gate region used when Frame Reset and VSYNC are both driven to a cam era from the PTG Bit Mnemonic Fun...

Page 99: ...3 Vgate start 2 0 lines after Vsync low 4095 0xFFF Vgate start 2048 lines after Vsync low 3 4 3 2 Vertical Gate End VGEND R W VGEND defines the duration of the Programmable Timing Generator PTG Vertic...

Page 100: ...tal PWGH R W 0 7 BADR2 0x10 HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0 8 15 HACT5 HACT4 HACT3 HACT2 HACT1 HACT0 HOFF9 HOFF8 PCP_PWGH_32 16 23 Reserved Reserved HACT11 HACT10 HACT9 HACT8 HACT7 HAC...

Page 101: ...counter on which to stop loading the memory The Programmable Window Generator PWG horizontal counter starts counting off the selected edge of Hsync HACT determines the number of pixel clocks to stop l...

Page 102: ...ve 22 EXTRIGSTAT0_15 15 pin TTL Trigger 0 Status 23 EXTRIGSTAT1_26 26 pin TTL Trigger 1 Status 24 EXTRIGSTAT0_26 26 pin TTL Trigger 0 Status 25 OPTOSTAT0 Opto isolator Trigger 0 Status 26 OPTOSTAT1 Op...

Page 103: ...of the first valid line start loading memory The memory loads all lines between VOFF and VACT Use the following formula to calculate VACT For interlaced images use number of lines per field and for n...

Page 104: ...input is 1 3 4 5 7 Opto Isolator Trigger 1 Status OPTOSTAT1 R O This read only bit reflects the status of the Opto isolator Trigger 1 input OPTOSTAT1 Status 0 Trigger input is 0 1 Trigger input is 1 3...

Page 105: ...with triggered acquisition Bit Mnemonic Function 0 TRIGEN Trigger Enable 1 3 TRIGSEL Trigger Source Select 4 TRIGPOL Trigger Polarity Select 5 TRIGCYC Trigger Cycle Status 6 SKPFLDMD Skip Field Mode 7...

Page 106: ...the PWGV register TRIGSEL Selected trigger input 0 Software trigger 1 15 pin TTL trigger input 0 2 26 pin TTL trigger input 1 3 26 pin TTL trigger input 0 4 Opto coupled trigger input 0 5 Opto coupled...

Page 107: ...it selects fast strobe or slow strobe mode The strobe pulse output is always one horizontal line duration In Fast Strobe mode a 1 line strobe output pulse occurs immediately after the external trigger...

Page 108: ...ay counter reaches the STRBDLY value a number of lines after trigger If the trigger occurs after the strobe delay counter reaches STRBDLY the strobe pulse is output imme diately after the trigger puls...

Page 109: ...on a separate pin FRSTONV Function 0 Vsync is vertical sync output 1 Vsync is Frame Reset output 3 4 6 15 Frame Reset Offset Duration FROFF R W FROFF defines a delay between the trigger pulse and the...

Page 110: ...atch enabled triggers that occur during a triggered acquisition are latched and another triggered acquire begins immediately following completion of the current triggered acquire cycle TRIGMD Function...

Page 111: ...INSEL Video Input Select 7 VSCLKSEL VSCAN Clock Select 8 OVRSM Oversample Input Mode Select 9 VCLKPOL Variable Scan Clock Input Polarity 10 LENPOL Line Enable Input Polarity Select 11 FENPOL Frame Ena...

Page 112: ...de CAM0 and CAM1 have separate CLK and Frame Reset pins If VSCLKSEL 0 the clock is input on the CLKIN0 and CLKIN1 pins If VSCLKSEL 1 the clock is input on the FRESET0 and FRESET1 pins TIMEMD Function...

Page 113: ...VCLKPOL R W The VCLKPOL bit can invert the incoming variable scan clock when PCVisionplus is in variable scan mode Inter nal circuits sample the video signal on the rising edge of the clock If your ca...

Page 114: ...lf line Vsync FEN must be greater than two horizontal line times to use generated field mode FLDSEL Function 0 Sync stripper field 1 Generated field 3 4 7 13 Field Shift Mode FLDSHFT R W This bit enab...

Page 115: ...on the 26 pin connector MISCOUTx Function 0 OUTx is low 1 OUTx is high 3 4 7 18 Misc Input MISCIN2 MISCIN1 MISCIN0 R O These three bits reflect the current state of the external inputs MISC_IO_IN2 MI...

Page 116: ...VBLANKINTSTAT Vertical Blank Interrupt Status 5 VBEVENINTSTAT Vertical Blank Odd Field Interrupt Status 6 VBODDINTSTAT Vertical Blank Even Field Interrupt Status 7 31 Reserved Don t care 3 4 8 1 Star...

Page 117: ...BLANKINTEN bit in the AM Interrupt Control register AMINTEN Writing one to this status bit clears the interrupt request VBLANKINTSTAT Status 0 No interrupt request pending 1 Vertical blank interrupt r...

Page 118: ...served Don t care 3 4 9 1 Start of Trigger Interrupt Enable SOTINTEN R W This bit enables an interrupt that occurs at the start of a triggered acquisition The input polarity is defined by the TRIGPOL...

Page 119: ...upt 1 Enable PWG Vertical Blank interrupt 3 4 9 6 Vertical Blank Even Field Interrupt Enable VBEVENINTEN R W The VBEVENINTEN bit enables an interrupt that occurs when the PWG vertical blank signal goe...

Page 120: ...RT0 CLMPSRC 8 15 BPEND7 BPEND6 BPEND5 BPEND4 BPEND3 BPEND2 BPEND1 BPEND0 PCP_PCLAMP_32 16 23 NO NO NO NO NO NO NO NO 24 31 Reserved Reserved Reserved CNTEN NO NO NO NO SRC CLAMP10 CLAMP9 CLAMP8 CLAMP1...

Page 121: ...clamp counters The CNTENSRC bit in this register selects which Hsync enables the clamp position counters Sync Stripper timing or timing selected by the TIMEMD bits The value of BPEND must be greater t...

Page 122: ...ster selects which Vsync enables the clamp position counters Sync Stripper timing or timing selected by the TIMEMD bits Use the Sync Stripper timing for standard RS170 and CCIR video sources The No Cl...

Page 123: ...gister and the PLLCS bit in the INCON2 register The PLL registers and programming examples appear in Chapter 4 3 4 13 DAC Programming Port DACPROG R W 0 7 BADR2 0x38 Reserved Reserved Reserved Reserve...

Page 124: ...care 3 4 14 1 Timer Count TIMERCNT R W The TIMERCNT bits define a starting value for the down counter Writing to this register immediately loads a new value into the counter and the count continues f...

Page 125: ...tatus 6 STRBINSTAT Input Port Strobe Input Status 7 31 Reserved Don t care 3 4 15 1 Output Port Strobe OUTSTB R W This bit determines the state of the Output Port Strobe signal STROBE_O This bit is cl...

Page 126: ...ed all zeros 3 4 15 5 Input Port Interrupt Polarity IPINTPOL R W This bit defines the edge used to register an interrupt input on the parallel port The PIOIEN bit enables the interrupt This bit is cle...

Page 127: ...uffer not the actual output pins This register is cleared during power up and system reset 3 4 17 PIO Input Port INPORT R O 0 7 BADR2 0x48 INP7 INP6 INP5 INP4 INP3 INP2 INP1 INP0 8 15 Reserved Reserve...

Page 128: ...ADC output bit 11 is connnected to LUT input bit 0 The Oversample Enable bit OVRSM controls the input LUT configuration which has a great affect on how the LUT is programmed The Input Data Format bit...

Page 129: ...he pixel data program the LUT to ignore the high byte input delayed pixel by repeating the same data pattern If you are oversampling program the LUT to average the values input on the two address byte...

Page 130: ...0x20 Segment Size SGSZ 0x24 0x28 0x2C 0x30 0x3FFFF OCT Start Address OCTSTART Reserved Interrupt Control INTENREG BADR3 3 74 3 75 3 77 3 79 Acquisition Start Address ACQSTRT 0x18 3 72 Reserved 0xC0010...

Page 131: ...ield Start Status 13 PREVFLDSTART Previous Field Start Status 14 AMVBSTAT Acquisition Vertical Balnk Status 15 AMFLDSTAT Acquisition Field Status 16 17 INMODE Input Data Format 18 31 Reserved Don t ca...

Page 132: ...memory and also indicate when an acquisition has ended ACQMD Function 0 Freeze stop acquire 1 Invalid 2 Snap single frame acquire 3 Grab continuous acquire These bits change immediately when they are...

Page 133: ...ld not be used to determine acquire status GSTAT Function 0 No acquire in progress 1 Acquire in progress 3 5 1 7 Field Start Status FLDSTART R O This status bit reflects which field an interlaced acqu...

Page 134: ...bytes or four pixels per DWORD In 8 bit mode the Input LUT must be pro grammed to output pixel data on bits 11 4 out of the LUT Bits 15 12 and 3 0 of the LUT output are ignored in 8 bit mode In 12 bit...

Page 135: ...Enable BMEN R W The BMEN bit enables the bus master port for a memory data transfer onto the PCI bus BMEN should be disabled prior to changing any of the other bus master settings to avoid affecting...

Page 136: ...us master Transfer Count must be adjusted for the zoom factor Double the transfer count for zoom by 2 Multiply the transfer count by four for zoom by 4 Half the transfer count for decimate by 2 Refer...

Page 137: ...ter controller and padding replaces the second replicated copy of each pixel with 0x80 in the upper byte of each WORD in the FIFO Zoom by 4 with pad mode produces a padded zoom by 2 horizontal image I...

Page 138: ...7FFF or 32767 3 5 3 Memory Initialization MEMINIT W O 0 7 BADR3 0x14 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 8 15 Reserved Reserved Reserved Reserved Reserved Reserved...

Page 139: ...a memory frame for writing or storing an acquired image The acquire start address is programmable on 128 byte boundaries If the image acquire reaches the maximum memory address 0x7FFFF DWORDs the acqu...

Page 140: ...18 LSBMASK Interrupt Address LSB Mask 19 31 Reserved Don t care 3 5 5 1 Acquire Interrupt Address INTADR R W The 12 bit Acquire Interrupt Line Address INTADR held in this register define a memory line...

Page 141: ...Size SGSZ R W 0 7 BMADR3 0x20 SGSZ7 SGSZ6 SGSZ5 SGSZ4 SGSZ3 SGSZ2 SGSZ1 SGSZ0 8 15 Reserved SGSZ14 SGSZ13 SGSZ12 SGSZ11 SGSZ10 SGSZ9 SGSZ8 PCP_SGSZ_32 16 23 Reserved Reserved Reserved Reserved Reserv...

Page 142: ...Start address 0xFFFF 3 5 8 Interrupt Status INTSTAT R W1C 0 7 BMADR3 0x28 Reserved Reserved Reserved Reserved EOFINT AMINT BMINT ACQLINE 8 15 Reserved Reserved Reserved Reserved Reserved Reserved Rese...

Page 143: ...Write Command 0 No interrupt No effect 1 Bus master interrupt request Clear interrupt request 3 5 8 3 AM Interrupt Status AMINTSTAT R W1C The AMINTSTAT bit indicates an interrupt is posted from AMINTC...

Page 144: ...OFINTEN End of Frame Interrupt Enable 4 31 Reserved Don t care 3 5 9 1 Acquire Line Interrupt Enable ACQLINEINTEN R W The ACQLINEINTEN bit enables an interrupt that occurs when the acquire operation w...

Page 145: ...into a memory buffer In multiple frame modes EOFINT will set for every frame of the multiple frame acquire operation EOFINTEN Function 0 Disable EOF interrupt 1 Enable EOF interrupt 3 5 10 Acquire Ad...

Page 146: ...dress 19 Reserved Don t care 20 23 XCNT Transfer Count 24 31 Reserved Don t care 3 5 11 1 Start Address ADR R W The 19 bit start address supports image buffers up to 4MB This address does not wrap at...

Page 147: ...00000 transfers more than the entire 4MB memory frame For example programming XCNT to 2048K DWORDs transfers the entire memory frame twice The PCVisionplus image memory is partitioned into 2048 byte p...

Page 148: ...gather table The even addresses contain PCI bus destination addresses The odd addresses contain transfer count values The Segment Size register SGSZ defines how many of these destination pointers are...

Page 149: ...stination Address MDSTADR 0xC0004 Add On Interrupt Control AINT 3 83 3 84 3 82 0xC0000 3 83 Figure 3 14 Add On Register Map 3 5 13 1 Add On Interrupt Control AINT W O 0 7 BADR3 0xC0000 DATA7 DATA6 DAT...

Page 150: ...alue to this address to transfer the value into the correct location 3 5 13 3 Manual Destination Address MDSTADR W O 0 7 BADR3 0xC0008 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 8 15 ADR15 ADR14 ADR13 AD...

Page 151: ...er is for diagnostic purposes only Writing a value into this register checks the BMC ability to load a trans fer count into the PCI bus Controller chip The BMEN bit in the BMCTLX register Frame Buffer...

Page 152: ...ATA bit in the DACPRG register DACSDATA performs both write and read back functions Reading the DACSDATA bit is used in diagnostics to verify the serial daisy chain is connected The internal DAC value...

Page 153: ...nd NREF DACs es tablish the positive and negative voltage references independently The absolute minimum difference between any PREF and NREF combination is 0 4 Volt The absolute maximum difference bet...

Page 154: ...h 2 5 8192 0 3 mV steps The default DAC setting for 1 75 Volts is 0x1666 5734 decimal Desired Clamp Level 1 75 V DAC value desired clamp voltage level 2 5 V 8192 1 75 0 000305 5734 0x1666 Data Output...

Page 155: ...gister while PLLCS is low in the INCON2 register set before accessing PLLPRG register The first bit loaded is the R W bit which is 0 to indicate the cycle is a write cycle Next three address bits A 2...

Page 156: ...iting the PLLPRG one more time Clk1 Clk14 Clk5 Clk4 Clk3 Clk2 Clk16 Clk15 PLLSCLK PLLCS PLLSDATA A0 A1 R Wbit A2 D0 D9 D10 Write Cycle PLLSDATA A0 A1 R Wbit A2 Read Setup Cycle PLLSDATA Input PLLSDATA...

Page 157: ...values 4 2 5 PLL Register 1 PLLA1 0 7 PLL Address 0x1 LO7 LO6 LO5 LO4 LO3 LO2 LO1 LO0 8 15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCR_PLLA1_16 Bit Mnemonic Function 7...

Page 158: ...10 REFPOL Reference Polarity 15 11 Reserved Don t care 4 2 7 1 Reference Divider RDIV R W These bits control the PLL reference divider Modulus which divides the XTAL EXTREF by the set modulus The modu...

Page 159: ...Enable 7 INTFLT Loop Filter Select 8 INTVCO VCO Select 9 CLKSEL Feedback Divider Clock Select 10 Reserved Must be one 15 11 Reserved Don t care 4 2 8 1 VCO Gain VCO R W These bits control the PLL VCO...

Page 160: ...Select INTFLT R W This bit selects between external and internal loop filter mode The PCVisionplus uses an external loop filter This bit should always be 0 Power up default setting is 1 which must be...

Page 161: ...4 2 9 1 Feedback Select FBKSEL R W This bit selects internal feedback mode of the PLL Default setting is 1 Always program this bit to one FBKSEL Function 0 External feedback not supported 1 Internal F...

Page 162: ...ram to 3 4 2 9 7 Fine Phase Adjust Lead Lag LDLG R W This bit sets the lead lag relationship at the input to the PFD programmable frequency detector Default setting is 1 Always use the default value o...

Page 163: ...XTREF EXTREF Select 15 11 Reserved Don t care 4 2 10 1 Load Counter LCOUNT R W These bits define the divide ratio of the PLL Load Counter Default setting is 7 Refer to the Examples for Program ming PL...

Page 164: ...to zero 4 2 10 7 Output Test Mode AUXEN R W This bit puts the PLL circuit into test mode for diagnostic purposes only This bit should always be zero 4 2 10 8 Output Clock for Test Mode AUXCLK R W Thi...

Page 165: ...me is 63 556 us and the active time is 52 656 us For CCIR the total line time is 64 us and the active time is 51 95 us 2 Determine PDA and LCOUNT Let ODA Output Divider Actual PDA x LCOUNT Find ODD Ou...

Page 166: ...0x400 RDIV 0 Rdiv 1 RDIV Rdiv 1 1 1 0 REF_POL 1 PLLA4 0x75 1xxx where xxx VCO calculated above VCO from VCO Gain calculation above PFD 0x3 PFD gain always set to 15uA 2pi rad PDEN 1 phase detector ena...

Page 167: ...l to Crop from start of active video region For RS 170 Active 52 656 us Hsync 4 7 us Back Porch 4 7 us For CCIR Active 51 95 us Hsync 4 7 us Back Porch 5 8 us NOTE The Active region must be divisible...

Page 168: ...pen sate for discrepancies First the HOFF and HACTIVE values can be changed to move the ACTIVE video window left or right and the video is then re checked If there is no combination of HOFF and HACTIV...

Page 169: ...us Fdesired 1 Pclk d _______ frequency in MHz For RS 170 the total line time is 63 556 us and the Active time is 52 656 us For CCIR the total line time is 64 us and the Active time is 51 95 us 2 Deter...

Page 170: ...3 Find Fdiv using the following formula Fdiv Total number of pixels in horizontal period 1 or Fdiv Fdesired Horizontal Line Rate Fdiv _____ _______ ______ Both give the same result Set the FDIV regist...

Page 171: ...0x44 0xxx where xxx LCOUNT bits for the value found in tables LCOUNT bit setting for value found in tables OMUX1 0 use default EXTREF 1 external reference Input operation 8 Calculate Window Generator...

Page 172: ...op Start 1 Vactive of lines per field frame Vsync of lines in Vsync Vblank of lines from Vsync to the start of active video Crop End of lines to Crop from the end of active video region Crop Start of...

Page 173: ...t num ber of samples per line frame are being captured Specifically check the start and end of the horizontal line and verify valid pixel data is present this can be done by saturating the video sourc...

Page 174: ...le rate but also the PTG sync outputs which are driven to the camera Large changes to Pclk will require recalculating all PTG settings based on the new Pclk value When driving the camera with internal...

Page 175: ...10 PDA bits 0x2 PDA value 2 PDA value LCNT value PDA x LCNT 2 3 6 2 4 8 2 5 10 2 6 12 2 8 16 2 10 20 PDA bits 0x1 PDA value 4 PDA value LCNT value PDA x LCNT 4 3 12 4 4 16 4 5 20 4 6 24 4 8 32 4 10 40...

Page 176: ...O capability in the form of 8 input and 8 output high drive TTL channels A jumper labeled I O Level on the PCVisionplus board sets the power up state of the parallel port outputs All parallel port ou...

Page 177: ...e Description 1 no connection 2 CAM0 Video input camera 0 3 Trig_In_0_15 Trigger 0 TTL Input this input is available on both video connectors 4 CLKIN_0 Clock Input camera 0 5 DGND0 Digital ground came...

Page 178: ...Opto Isolator negative input 10 Opto_In1 Trigger 1 Opto Isolator negative input 11 AGND Camera ground 12 CLKIN_1 Clock Input camera 1 13 FRESET1 Frame reset camera 1 optional VSCAN clock input 1 14 12...

Page 179: ...o connection 11 STROBE_O Strobe Output Output data latch 13 STROBE_I Strobe Input Input data latch 15 I O_INT Interrupt Input 17 IN7 Digital Input pin 7 19 IN6 Digital Input pin 6 21 IN5 Digital Input...

Page 180: ...nector and a 26 pin connector for Miscellaneous interface signals 509 00066 00 509 00066 00 PCVisionplus Miscellaneous cable Converts 26 pin D Sub to 8 BNC connectors and 4 pairs of wire hookup connec...

Page 181: ...s Input 1 Misc_IO_In1 4 5 Miscellaneous Output 1 Misc_IO_Out1 5 6 Strobe 0 output Strobe_0 6 7 Strobe 1 output Strobe_1 7 8 Trigger 0 Opto positive input Opto_In0 8 9 Trigger 0 Opto negative input Opt...

Page 182: ...out Cable STROBE1 TTL_TRIG0 TTL_TRIG1 MISC_IN0 MISC_OUT0 OPTO_IN1 509 00065 00 PCVisionplus STROBE0 OPTO_IN0 6 ft DIFF_IN1 DIFF_IN0 MISC_OUT1 MISC_IN1 26 pins all shields connected to digital ground O...

Page 183: ...G0 Trigger 0 TTL input Trig_In0_26 17 TTL_TRIG1 Trigger 1 TTL input Trig_In1 18 all shells Cable Shield Digital Ground 3 24 Wire Label OPTO_IN1 Trigger 1 Opto isolator positive input 1 OPTO_IN1 Trigge...

Page 184: ...ble This cable is also used with the Cidtec 2250 and 3750 cameras in non interlaced RS 170 compatible mode Table A 7 ACBL BNC Cable Pin Out BNC Label Signal Description 15 pin CAMERA Video input singl...

Page 185: ...l sync 13 7 VDRIVE Vertical sync 14 8 Digital ground 5 9 no connection or CLKIN_0 see note 4 10 no connection 11 no connection 12 Digital ground 5 4607 15 pins 12 pins 6 ft Figure A 5 ACBL HIR1 Adapto...

Page 186: ...ion 15 pin 1 12 Return 10 2 12 Volts DC 15 3 Analog ground 7 4 Video input single ended 2 5 no connection 6 no connection 7 VDRIVE vertical sync 14 8 Digital ground 5 9 HDRIVE composite horizontal syn...

Page 187: ...12 Volt return 10 2 12 Volts DC 15 3 Analog ground 7 4 Video input single ended 2 5 Digital ground 5 6 HDRIVE horizontal sync 13 7 VDRIVE Vertical sync 14 8 Digital ground 5 9 10 no connection 11 12...

Page 188: ...rammed to input the Clock on the Frame Reset pin Table A 11 ACBL VSCAN Cable Pin Out 12 Pin Signal Description 15 pin 1 12 Volt return 10 2 12 Volts DC 15 3 Analog ground 7 4 Video input single ended...

Page 189: ...402 00005 00 Video Connections A 14 Rev 02 February 8 2002 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 190: ...to Isolator The PCVisionplus uses the HPCL 0631 for its opto isolatoed trigger input Chapter 1 lists the recommended operat ing current and voltage values Do not exceed the absolute maximum ratings of...

Page 191: ...is connected to your logic or signal and the negative input is connected to ground through a resistor 330 ohm 1 8 Watt shown The resistor limits current through the diode The external resistor 1 K oh...

Page 192: ...c or trigger 1 8 Watt Relay pullup Vcc or PWR Current Sinking Output Current Sourcing Output 2 2 K ohm Value Vcc or trigger 2 2 K ohm Value Vcc or trigger Connecting to a Connecting to a V dc Output O...

Page 193: ...on and the transistor is turned on When the output is zero the diode and the transistor are off 330 ohm output output PCVisionplus output signal 1K ohm 1 8 Watt Figure B 4 Opto Coupled Output Circuit...

Page 194: ...5 ADC 2 17 reference voltage 2 17 reference voltage DACs 4 2 ADD add 1 VCO cycle PLL 4 10 address DMASTART DMA start address 3 71 ILUTSADR input LUT static address 3 48 ADR start address OCT 3 79 alia...

Page 195: ...68 scanning direction SCANDIR 3 70 transfer count status BMXC 3 18 transfer done BMDONE 3 22 bus master transfer specification 1 6 C cables A 5 adapter A 9 break out A 5 cache line size CALN 3 11 CALN...

Page 196: ...done bus master transfer BMDONE 3 22 DPARE detected parity error 3 10 DPDATA scatter gather data register 3 81 DTPAR data parity reported 3 9 E EDON E Donpisha mode enable 3 30 enable BMSHIFT bus mast...

Page 197: ...21 filter select LPFSEL low pass filter select 3 45 FINEEN PLL fine phase adjust enable 4 11 FLDPOL field input polarity 3 47 FLDSEL field source select 3 47 start field select 3 65 FLDSHFT field shif...

Page 198: ...45 input strobe enable IENREG_ENB 3 58 INREG_CLR input buffer clear parallel port input 3 59 INREG_ENB input buffer enable 3 58 INSTB_POL input strobe polarity 3 59 INTADR acquire interrupt address 3...

Page 199: ...access 3 61 look up tables 2 18 low WORD access 3 61 static address ILUTSADR 3 48 LUT programming 3 61 M MAINT master abort interrupt status 3 20 mapping AM control registers BADR2 3 13 board ID regi...

Page 200: ...le INTEN 3 19 PCI configruation registers 2 2 PCI configuration registers 3 6 PCI interface control registers 2 3 PCI bus interface overview 1 1 interrupts 2 3 PCIBMEN bus master enable 3 8 PCICMD PCI...

Page 201: ...er 3 29 PTGV2 PTG vertical timing register 3 31 PWG in PLL mode 2 29 programmable window generator 2 29 variable scan mode 2 31 XTAL mode 2 31 PWG vertical timing 2 32 PWGH PWG horizontal timing regis...

Page 202: ...35 reference DAC programming 4 1 RID revision ID 3 11 SGSZ segment size 3 74 SOFTTRIG software trigger 3 53 STRBDLY strobe delay 3 41 TIMER software counter timer 3 57 VID vendor ID 3 6 XROM expansion...

Page 203: ...us 3 36 3 37 EXTRIGSTAT1 TTL trigger 1 input status 3 36 FIFO 4 plus FIFO4P 3 21 FIFO empty FIFOEM 3 22 FIFO full FIFOFL 3 21 FPGARDY FPGA load complete 3 24 FSTRT start field 3 66 INPORT_INT parallel...

Page 204: ...ut specification 1 2 timing output specification 1 4 transfer count status BMXC 3 18 XCNT OCT 3 80 TRGCYC trigger cycle status 3 40 TRIGEN trigger enable 3 39 trigger bact to back 2 36 cycle status TR...

Page 205: ...VID vendor ID register 3 6 video input field status AMFLDSTAT 3 67 specification 1 2 vertical blank status AMVBSTAT 3 66 video inputs AM control mapping BADR2 3 13 VIDEOINSEL video input select 3 45...

Page 206: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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