DAC and PLL Programming
PCVisionplus
Hardware Reference
4–5
Rev 02; February 8, 2002
Notice the difference between the 15 reg writes in a write cycle and the 15 reg reads in a read cycle. During the read,
the first clock is associated with valid data (A0), but in a write the first clock is associated with the R/W bit. Due to
this different alignment, the three address bits and the 11 data bits are read with the first 14 clocks (last data D10 is
read out with the 14th clock). However a 15th clock is still required with PLLCS low, which disables the read com-
mand. After the 15th read, discard this data and bring the cycle to an end as shown, by bringing PLLCS high and
executing a final 16th clock by writing the PLLPRG one more time.
Clk1
Clk14
Clk5
Clk4
Clk3
Clk2
Clk16
Clk15
PLLSCLK
PLLCS
PLLSDATA
A0
A1
R/Wbit
A2
D0
D9
D10
Write Cycle
PLLSDATA
A0
A1
R/Wbit
A2
Read Setup Cycle
(PLLSDATA Input)
PLLSDATA
A0
A1
A2
D0
D10
Dummy
Read Cycle
(PLLSDATA Output)
Load Address For Read
Command Executed
Notes:
1. R/Wbit, READ=1 and WRITE=0
2. Address and Data transmitted Least Significant bit first.
3. Read or write of PLLPRG register causes PLLSCLK.
16 Positive-edge clocks required for complete data read/write.
(1 - R/Wbit, 3 - Address bits, 11 - Data bits, and 1 load data (set PLLCS high
and execute a dummy read or write to PLLPRG register))
4. A read cycle consists of two consecutive cycles (1st a write
cycle loads the address to be read and 2nd a read of the shift
register is executed)
Figure 4–1. PLL Serial Programming Timing
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