PCVisionplus
Hardware Reference
Index
Index–3
Rev 02; February 8, 2002
conventions, iv
count
FCNT, frame count, 3–65
timer register, TIMERCNT, 3–57
counter source, CNTENSRC, clamping counter enable, 3–55
crop
half lines, FLDSHFT, 3–47
HOFF, horizontal offset, 3–34
vertical offset, VOFF, 3–35
cropping, half lines, field shift, 2–33
CSC option, BLDSTAT, build status, 3–24
D
DAC
programming, 4–1
registers, 4–1
serial data, DACSDATA, 3–56
sync stripper line rate, 4–3
DACCS, DAC chip select, 3–45
DACPROG, DAC programming register, 3–56
DACSDATA, DAC serial data, 3–56
data
INMODE, input data format, 3–67
serial PLL, PLLSDATA, 3–56
data strobe, parallel output, OUTSTB, 3–58
DC restoration, 2–16
decimate, 2–8
delay
frame reset offset, FROFF, 3–42
strobe, STRBDLY, 3–41
destination, BMDST, bus master destination address status, 3–18
diagram
input termination, 2–15
timing
LEN/FEN/FIELD, 1–3
set up and hold, 1–3, 1–4
DID, device ID register, 3–6
DIFFSTAT0, differential trigger 0 input status, 3–37
DIFFSTAT1, differential trigger 1 input status, 3–37
DMA Table, segment size register, SGSZ, 3–74
DMA table
(scatter gather table), 2–8
specification, 1–5
DMASTART, DMA start address, 3–71
done, bus master transfer, BMDONE, 3–22
DPARE, detected parity error, 3–10
DPDATA, scatter gather data register, 3–81
DTPAR, data parity reported, 3–9
E
EDON, E–Donpisha mode enable, 3–30
enable
BMSHIFT, bus master data shift enable, 3–68
clipping, CLIPEN, 3–70
E–Donpisha mode, EDONP, 3–30
frame reset mode, FRSTMD, 3–41
I/O space access, IOEN, 3–7
interrupt, PIOIEN, I/O port interrupt enable, 3–52
memory space access, MEMEN, 3–7
padding, PADEN, 3–70
parity error, PAREN, 3–8
phase frequency detector gain, PDEN, 4–9
programmable clamp, CLMPSRC, 3–54
skip field mode, SKPFLDMD, 3–40
strobe output, STRBEN, 3–41
system error, SEREN, 3–8
transfer done interrupt, BINTEN, 3–20
trigger, TRIGEN, 3–39
VBEVENINTEN, vertical blank even field interrupt enable, 3–52
VBLANKINTEN, vertical blank interrupt enable, 3–52
VBODDINTEN, vertical blank odd field interrupt enable, 3–52
vertical sync output, VSYNCEN, 3–47
WEN mode, WENMD, 3–40
end
BPEND, back porch clamp position, 3–55
vertical gate, VGEND, 3–32
end of frame, interrupt enable, EOFINTEN, 3–78
EOFINTEN, end of frame interrupt enable, 3–78
EOFINTSTAT, end of frame interrupt status, 3–76
EOTIEN, end of trigger interrupt enable, 3–51
EOTINT, end of trigger interrupt status, 3–49
error
parity error enable, PAREN, 3–8
system error enable, SEREN, 3–8
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