402-00005-00
Theory of Operation
2–26
Rev 02; February 8, 2002
programmable timing generator (PTG) and programmable window generator (PWG) use the sync stripper output for
locking to and framing incoming video.
The sync stripper can be bypassed by selecting separate sync as the input to the PLL. In bypass mode, sync signals are
input separately from CAM0 or CAM1 and are used by the programmable timing generator (PTG) and program-
mable window generator (PWG) for locking to and framing incoming video.
The sync stripper features a programmable horizontal line rate, from 15 KHz to 66.5 KHz. This provides support for
non-standard horizontal line rates in PLL mode, such as the JAI M30 camera with a 32 KHz line rate. The line rate is
controlled by a 13-bit DAC. The horizontal line rate is inversely proportional to the DAC voltage, as shown in Figure
2–25. The formula for calculating the Sync Stripper DAC value is:
NB = (1.7 – (line rate in KHz) / 45 KHz) ) / 0.000169
Where NB is the programmed 13-bit DAC value.
35.6 KHz
66.5 KHz
56.2 KHz
49.5 KHz
25.3 KHz
15 KHz
4914.6
4095.5
3276.4
2457.3
1638.2
819.1
8191
7371.9
6552.8
5733.7
Figure 2–25. Sync Stripper Line Rate
2.7.3 Phase-Locked Loop
The Phase-Locked Loop (PLL) performs both the line locking function of the standard PLL mode and the frequency
synthesis function of internal clock (XTAL) mode. The mode of operation affects the PLL programming. The PLL is
programmed through a serial interface, described in the Chapter 4. Figure 2–26 illustrates the PLL/XTAL clock gen-
erator.
For PLL operation, the internal PLL feedback path selects the PLL clock output signal (selected by CLKSEL). The
feedback path is programmed to divide the PLL clock to equal the incoming horizontal line frequency. The reference
divider is 1 in PLL mode. The feedback path is input to the phase detector and compared to the selected PLL Hsync
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