PCVisionplus
Hardware Reference
Index
Index–5
Rev 02; February 8, 2002
grab, ACQMD, acquire command, 3–65
GSTAT, grab status, 3–66
H
HACT, horizontal active, 3–34
hardware switches, variable scan signals, 2–24
HDR, header type, 3–12
header type, HDR, 3–12
HESYNC, horizontal sync low end, 3–28
HI, feedback sync pulse high, PLL, 4–7
HOFF, horizontal offset, 3–34
horizontal
active size, HACT, 3–34
line rate, HTOTAL, 3–27
offset, HOFF, 3–34
sync low time, HESYNC, 3–28
sync polarity, HSYNCPOL, 3–28
sync polarity into PWG, XTALMDHPOL, 3–28
host access, specification, 1–6
host interface, 2–1
HSYNCPOL, horizontal sync polarity, 3–28
HTOTAL, horizontal line rate, 3–27
humidity, specification, 1–7
I
ILUTSADR, input LUT static address, 3–48
image acquisition, into image memory, 2–5
image memory, mapping, BADR4, 3–14
INCON1, input control register, 3–38
INCON2, input control register, 3–44
INMODE, input data format, 3–67
INPORT, input port register, 3–60
INPORT_INT, input port interrupt status, 3–59
INPORT_IPOL, input port interrupt polarity, 3–59
input, opto–isolator circuits, B–2
input buffer, clear, INREG_CLR, parallel port input, 3–59
input clamping, DC restoration, 2–16
input conditioning, 2–14
input gain, 2–14
input LUT, 2–18
input MUX, 2–14
input resistance, 2–14
input select, VIDEOINSEL, 3–45
input strobe, enable, IENREG_ENB, 3–58
INREG_CLR, input buffer clear, parallel port input, 3–59
INREG_ENB, input buffer enable, 3–58
INSTB_POL, input strobe polarity, 3–59
INTADR, acquire interrupt address, 3–73
INTCTL, PCI interrupt control status, 3–19
INTEN, PCI interrupt enable, 3–19
INTENREG, interrupt control register, 3–77
interface, to host, 2–1
interface control
register map, 3–3
registers, 3–3, 3–17
interface control registers, mapping, BADR0, 3–12
interlace, input scan mode, SMODE, 3–47
internal timing, synchronization, 2–22
interrupt
AM control register, AMINTEN, 3–51
bus master transfer done, BINTEN, 3–20
enable, EOFINTEN, end of frame interrupt enable, 3–78
EOTIEN, enable end of trigger interrupt, 3–51
INTADR, acquire line address, 3–73
INTCTL, PCI interrupt status, 3–19
PIOIEN, I/O port interrupt enable, 3–52
polarity, INPORT_IPOL, parallel port interrupt input, 3–59
SOTIEN, enable start of trigger interrupt, 3–51
status, INPORT_INT, parallel port interrupt input, 3–59
VBEVENINTEN, vertical blank even field interrupt enable, 3–52
VBEVENINTSTAT, vertical blank even field interrupt status, 3–50
VBLANKINTEN, vertical blank interrupt enable, 3–52
VBLANKINTSTAT, vertical blank interrupt status, 3–50
VBODDINTEN, vertical blank odd field interrupt enable, 3–52
VBODDINTSTAT, vertical blank odd field interrupt status, 3–50
interrupt enable
acquire line, ACQLINEINTEN, 3–77
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