PCVisionplus
Hardware Reference
Theory of Operation
2–21
Rev 02; February 8, 2002
2.6.2 Separate Sync PLL mode
The PCVisionplus also supports PLL mode with separate horizontal and vertical sync inputs from cameras CAM0 or
CAM1. The sync stripper is not used and the separate incoming timing signals drive the PLL and PWG directly as
shown in Figure 2–21. Separate sync inputs must be referenced to ground. Analog or negative-going sync inputs are
not supported in this mode. The polarity of the sync inputs is programmable, allowing positive or negative polarity
input (active-high or active-low signals).
Separate HSYNC Input
ADC
PLL
PWG
V
H
PLL Clock
Memory Load
Timing
Separate VSYNC Input
non-Composite Video
Figure 2–21. PLL Mode with Separate Syncs
As shown in Figure 2–21, the PLL compares the separate horizontal sync input to internal feedback, and generates
the PLL clock. The ADC uses the PLL clock to digitize the video input. Program the PWG for the desired video
frame; full frame or AOI. The PWG uses the PLL clock and the horizontal and vertical input signals to frame the
video output.
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