402-00005-00
Registers
3–22
Rev 02; February 8, 2002
3.2.5.3 FIFO Empty (FIFOEM) R-O
This bit is set to one when the FIFO becomes empty, during a bus master transfer from the PCVisionplus to the PCI-
bus. FIFO empty indicates data is not available for transfer during a bus master cycle. This bit is read only.
FIFOEM
Function
0
FIFO is not empty
1
FIFO is empty
3.2.5.4 Bus Master Done (BMDONE) R-O
This bit is set to one when a bus master transfer from the PCVisionplus to the PCI-bus completes. Completion of a
bus master cycle is when the value in the Bus Master Transfer Count register reaches zero. This bit is read only.
BMDONE
Function
0
Bus master cycle not done
1
Bus master cycle done
3.2.5.5 Software Reset (RST) R/W
This bit can be used by software to reset the PCVisionplus internal hardware. Writing a one to this bit causes a reset to
the PCVisionplus. This bit must be set to zero to remove the reset for proper operation of the PCVisionplus.
RST
Function
0
No reset
1
Reset the PCVisionplus
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