402-00005-00
Index
Index–4
Rev 02; February 8, 2002
examples
programming PLL mode, 4–14
programming XTAL mode, 4–18
external trigger, operation, 2–34
EXTREF, PLL external reference select, 4–13
EXTRIGSTAT0, TTL trigger 0 status, 3–36, 3–37
EXTRIGSTAT1, TTL trigger 1 status, 3–36
F
fast strobe, 2–37
FBB, fast back–to–back enable, 3–8
FBKPOL, PLL feedback polarity select, 4–10
FBKSEL, PLL feedback select, 4–10
FCNT, frame count, 3–65
FDIV, PLL feedback divider, 4–6
feedback
divider, PLL, FDIV, 4–6
mode select, PLL, FBKSEL, 4–10
PLL divider sync pulse high, HI, 4–7
PLL divider sync pulse low, LO, 4–6
polarity select, PLL, FBKPOL, 4–10
post scaler, PLL, PDB, 4–11
feedback divider, PLL clock select, CLKSEL, 4–9
field
FLDSEL, start field select, 3–65
polarity, FLDPOL, 3–47
PREVFLDSTART, previous start field status, 3–66
shift mode, 2–33
skip, SKPFLDMD, 3–40
source select, FLDSEL, 3–47
start status, FSTRT, 3–66
status, AMFLDSTAT, 3–67
field shift, FLDSHFT, cropping 1/2 lines, 3–47
FIFO4P, FIFO 4 plus, 3–21
FIFOEM, FIFO empty, 3–22
FIFOFL, FIFO full, 3–21
filter select, LPFSEL, low–pass filter select, 3–45
FINEEN, PLL fine phase adjust enable, 4–11
FLDPOL, field input polarity, 3–47
FLDSEL
field source select, 3–47
start field select, 3–65
FLDSHFT, field shift mode, cropping 1/2 lines, 3–47
format, INMODE, input data format, 3–67
formatting, data output, 2–8
FPGA
load port, ORCAPRGM, 3–25
reset, ORCARST, 3–25
FPGADONE, FPGA load done, 3–24
FPGARDY, FPGA ready status, 3–24
frame buffer control
register map, 3–5
registers, 3–5
frame buffer control registers, 2–3, 3–63
mapping, BADR3, 3–14
frame count, FCNT, 3–65
frame rate, vertical sync total, VTOTAL, 3–29
frame reset, 2–38
mode, 3–41
offset, FROFF, 3–42
output on Vsync output, FRSTONV, 3–42
polarity, FRSTPOL, 3–42
size (pulse length), FRSTSZ, 3–42
WEN mode, WENMD, 3–40
freeze, ACQMD, acquire command, 3–65
frequency
detector gain, PFD, 4–9
detector gain enable, PDEN, 4–9
FROFF, frame reset offset, 3–42
FRSTMD, frame reset mode, 3–41
FRSTONV, frame reset on Vsync output, 3–42
FRSTPOL, frame reset polarity, 3–42
FRSTSZ, frame reset size (pulse length), 3–42
FSTRT, field start status, 3–66
G
gain
input, 2–14
phase frequency detector, PFD, 4–9
VCO gain, VCO, 4–8
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