402-00005-00
DAC and PLL Programming
4–4
Rev 02; February 8, 2002
4.2 PLL REGISTERS
PCVisionplus contains a PLL (Phase Lock Loop) for line locked clock operations (PLL mode) and for frequency
synthesis (XTAL mode). The PLL internal registers are accessed through a serial interface.
4.2.1 PLL Interface
The PLLCS bit in the INCON2 register and the PLLPRG register program the PLL. Holding the PLLCS bit low puts
the PLL in programming mode. Every access to the PLLPRG register (read or write) will generate a serial clock to
the shift data in or out of the PLL registers, depending on the cycle type. Read and write access is available on the
PLL serial port. Data is loaded in the lsb (least significant bit) of the PLLPRG register.
Every access to the PLL requires sixteen register reads/writes to the PLLPRG register, as shown in the Figure 4–1.
First the PLLCS bit must be set low, followed by the sixteen PLLPRG register cycles. The PLL has seven 11-bit
registers which are accessed by writing the appropriate value into the address bits A(2–0) bits. All registers must be
setup for proper PLL or XTAL mode operation. Single bit changes can be made by addressing the appropriate PLL
register and writing only 11-bits of data; it is not required to reload all PLL registers every time, but all 11 bits in one
register must be loaded.
NOTE
Use the IFC library functions to program the PLL registers. These functions are written to handle
the timing and protocol of this serial interface.
4.2.2 PLL Serial Write Cycles
PLLSDATA is loaded into an internal PLL shift register on every write of the PLLPRG register while PLLCS is low
(in the INCON2 register; set before accessing PLLPRG register). The first bit loaded is the R/W bit which is 0 to
indicate the cycle is a write cycle. Next, three address bits A(2–0) are loaded, which point to one of seven PLL inter-
nal registers. Finally, 11 data bits are loaded. The PLLCS bit must then be set high in the the INCON2 register, fol-
lowed by a dummy read or write access to PLLPRG register which performs the actual transfer of the 15-bit shift
register data into the addressed PLL register (PLLSDATA is “don’t care” for the dummy operation). 15 register
writes are required with PLLCS low and 1 register write is required after PLLCS is written high.
4.2.3 PLL Serial Read Cycles
Read cycles require two operations. First, a write must be executed as described in previous section with the R/W bit
high, to indicate a read cycle. The three address bits are loaded followed by 11 bits of ”don’t care” data (only need the
R/W bit and three address bits, but you must clock the PLLSCLK 11 more times to move the serial data into the
correct position in the internal 15-bit shift register). Write PLLCS high in the INCON2 register and execute a
dummy read or write to PLLPRG register, which loads the Read command and the selected address. At the end of the
dummy cycle, the Serial Data becomes an output and the contents of the addressed register are loaded into the shift
register (3 address bits and 11 data bits). To complete the read cycle, reset the PLLCS bit low and execute 15 read
cycles to PLLPRG. Each read will shift one bit out of the PLL internal shift register. After all bits are read, set PLLCS
high and execute one last dummy cycle to PLLPRG to end the read cycle.
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