402-00005-00
Theory of Operation
2–2
Rev 02; February 8, 2002
Timing
Control
Window
Generator
(PTG)
Camera 0
Camera 1
Input
MUX
Trigger inputs
Strobe outputs
32 by 8
FIFO
Memory
Address
Bus Master
Control
Scatter
Gather
Table
Bus Target
Control
Control
Registers
PCI Bus
Parallel
I/O
timing
data
12
Memory
4MB
ADC
Input
Conditioning
Input LUT
16
Figure 2–1. PCVisionplus Block Diagram
2.2.2 Register Access
The PCVisionplus registers are organized as five groups, each having different control over the board operation. All
five sets of registers must be properly initialized for operation of PCVisionplus.
2.2.2.1 PCI Configuration Registers
The PCI Configuration Registers are required for compliance with the PCI Specification. These registers are loaded
by a boot PROM with information about the PCVisionplus, (memory size, register size, type of device) which the
PCI-bus host uses, in conjunction with information from all other PCI-bus devices in the system, to determine an
optimum configuration. All configuration information is contained in these registers. No address jumpers or
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