PCVisionplus
Hardware Reference
Theory of Operation
2–3
Rev 02; February 8, 2002
switches are required on the PCVisionplus. Access to these registers is accomplished through special PCI-bus con-
figuration cycles. A separate base address is not required for this register set.
2.2.2.2 PCI Interface Control Registers
The PCI Interface Control Registers control bus transfer configuration, interrupt configuration, and mailbox opera-
tions. These registers require a separate base address which is determined by the system on power-up and written
into the Base Address Zero Register (BADR0) of the Configuration register set. Software can determine the base
address of these registers by executing a configuration register read cycle to the BADR0 register.
2.2.2.3 Board ID Registers
The Board Identity registers contain the build status and board revision information, and load the FPGAs (field pro-
grammable gate arrays). These registers require a separate base address which is determined by the system on power-
up and written into the Base Address One Register (BADR1) of the Configuration register set. Software can deter-
mine the base address of these registers by executing a configuration register read cycle to the BADR1 register.
2.2.2.4 Acquisition Module Control Registers
The Acquisition Module (AM) Control registers control the camera interface and timing. These registers require a
separate base address which is determined by the system on power-up and written into the Base Address Two Regis-
ter (BADR2) of the Configuration register set. Software can determine the base address of these registers by execut-
ing a configuration register read cycle to the BADR2 register. The input LUT is mapped with these registers.
2.2.2.5 Frame Buffer Control Registers
The Frame Buffer Control Registers control image memory frames, interrupts, image acquisition, scatter gather
table, output control table, and the bus master controller. These registers require a separate base address which is
determined by the system on power-up and written into the Base Address Three Register (BADR3) of the Configura-
tion register set. Software can determine the base address of these registers by executing a configuration register
read cycle to the BADR3 register.
2.2.3 PCI-bus Interrupts
PCVisionplus provides the capability to generate a PCI-bus interrupt based on various events. All interrupts are com-
bined and sent to the PCI-bus as a single interrupt signal.
Interrupts can be broken down into several categories: Acquisition interrupts, Frame Memory Interrupts, Bus Mas-
ter Interrupts, and PCI interface interrupts. Several levels of control are required for these different sets of interrupts.
Common to all interrupts are two registers found in the PCI Configuration register set: Interrupt Line (INTLN) and
Interrupt Pin (INTPIN). INTPIN is initialized on power up to define the PCI-bus interrupt pin used by PCVisionplus
as #INTA (this is required for PCVisionplus). The INTLN register is initialized to select the system interrupt line.
On the next level, in the PCI Interface Control Register Set is a register called Interrupt Control Status (INTCTL_32)
register, which enables and monitors all interrupts. Within the INTCTL_32 register is a bit (INTEN) common to all
interrupts, which must be set for any source to generate a PCI-bus interrupt. In addition, there are two control regis-
ters used for acquisition interrupt control and source selection.
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