402-00005-00
Theory of Operation
2–4
Rev 02; February 8, 2002
2.2.3.1 Master/Target Abort Interrupts
Once the configuration register INTLN and the INTEN bit in the INTCTL_32 register are initialized, the BMC mon-
itors all PCI-bus transactions and generate an interrupt if it encounters either a Master or Target Abort. Master Abort
occurs when the PCVisionplus attempts to transfer data to a non-existent or disabled Target. Target Abort occurs
when the PCVisionplus, in the process of a bus master transfer, encounters a target abort response from the destina-
tion of the transfer operation (typically indicating some sort of error in the transfer). These two interrupt sources are
always enabled if INTEN is set, and can be monitored or cleared by two bits (MAINT and TAINT) in the
INTCTL_32 register.
2.2.3.2 Bus Master Transfer Interrupts
PCVisionplus can be configured to generate an interrupt when a bus master transfer has completed. When the Bus
Master Transfer count (BMXC_32) decrements to zero, only the current segment transfer is complete, not the whole
transfer. The BMINT bit in the INTSTAT register indicates the last segment transfer is complete (end of scatter gath-
er table entries).
2.2.3.3 Acquisition Interrupts
PCVisionplus has multiple acquisition related interrupt sources. start of trigger cycle, end of trigger cycle, hardware
timer/counter, parallel I/O port interrupt input, acquire address, vertical blank (even, odd or any) and end of frame
are all sources available to generate PCI-bus interrupts. The INTLN register and the INTEN bit of the INTCTL_32
register must both be set properly for any of the sources. The AMINTEN and INTENREG registers enable the inter-
rupt sources. The AMINTCLR and INTSTAT registers contain status bits for all interrupt sources. Interrupt sources
with an enable bit in the AMINTEN register require two levels of enabling and monitoring. In addition, the
INTCTL_32 register contains an enable bit (INTEN) required to enable all PCVisionplus interrupts, and status bit
(INTST). The following order of setting and clearing acquisition interrupts must be followed:
•
Set the desired interrupt source(s) in the AMINTEN and INTENREG registers.
•
Set the INTEN bit in the INTCTL_32 register (required for all interrupts)
•
Clear any pending acquisition interrupt by writing the INCLR bit in the BMCTL_32 register to one.
•
Clear the interrupt status bits in the AMINTCLR and INTSTAT registers (by writing all ones) to eliminate any
previous interrupts.
•
Once an interrupt occurs, read the INTCTL_32 register (INTST bit will be set if the source(s) selected in the IN-
TENREG and AMINTEN registers caused the interrupt) the INTSTAT register and the AMINTCLR register
•
Once it is determined (from the status bits in INTSTAT and AMINTCLR) that an acquisition interrupt occurred,
first clear the status bit in AMINTCLR, then clear the status bit in INTSTAT, and then clear the INTST bit in the
INTCTL_32 register.
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