402-00005-00
Registers
3–54
Rev 02; February 8, 2002
3.4.11.1 Clamp Pulse Source (CLAMPSRC) R/W
The CLAMPSRC bit determines which clamp pulse performs the DC restoration. The programmable clamp pulse is
recommended for variable scan (VSCAN) and internal timing (XTAL) modes. The sync stripper clamp pulse is usu-
ally only available for PLL mode. You can use the sync stripper if a composite sync signal is available with the vari-
able scan timing or from a camera using internal timing.
CLMPSRC
Function
0
Sync Stripper Clamp Pulse
1
Programmable Clamp Pulse
3.4.11.2 Back Porch Start Position (BPSTRT) R/W
The seven BPSTRT bits define the start of the programmable clamp pulse, used for DC restoration (clamping) during
the “back porch” of the video signal. The start of the clamp pulse is a number of clocks from the beginning of the
Hsync pulse (falling edge of HSYNC, assuming an active low horizontal sync). The 14.318 MHz crystal in the Fre-
quency Synthesizer (PTG) drives the programmable clamp counters. The CNTENSRC bit in this register selects
which Hsync enables the clamp position counters: Sync Stripper timing or timing selected by the TIMEMD bits. The
value of BPEND must be greater than the value of BPSTRT.
The start and end count positions must not fall within the worst case margins for the external video variance and the
internal circuit. Every camera or video source has slightly different timing, and calculations must accommodate the
worst case possibilities. Refer to the RS170 and CCIR signal specifications for the margins of error for the actual
positions of the front porch and back porch. There is a fixed delay of three clock periods from the falling edge of
Hsync to the start of the back porch counters. Re-syncing of the PCVisionplus internal circuitry adds a margin of
error of one clock period of the crystal clock (69.84 ns) used to control the clamp circuit.
BPSTRT
Typical Start Position
Worst Case Start Position
0
(3 + 0) x 69.84 ns
(4 + 0) x 69.84 ns
1
(3 + 1) x 69.84 ns
(4 + 1) x 69.84 ns
2
(3 + 2) x 69.84 ns
(4 + 2) x 69.84 ns
. . .
. . .
. . .
127
(3 + 127) x 69.84 ns
(4 + 127) x 69.84 ns
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