PCVisionplus
Hardware Reference
3–1
Rev 02; February 8, 2002
CHAPTER 3
REGISTERS
This chapter provides a detailed description of all PCVisionplus registers and bits. The PCVisionplus contains five
separate register groups: PCI Configuration Registers, PCI Interface Control Registers, Board ID Registers, Ac-
quisition Control Registers, and Frame Buffer Registers. All registers support 32-bit access only.
The PCI Configuration Registers are required for PCI compliance and are located at predetermined address offsets.
The PCI Interface Control Registers, Board ID Registers, Acquisition Control Registers, and Frame Buffer Control
Registers each have a separate base address within the host system address region. Each base address is determined
by the system on power up and loaded into the Base Address Zero, One, Two, and Three registers (BADR0, BADR1,
BADR2, BADR3).
Figure 3–1 shows the mapping of the PCI Configuration Registers. Figure 3–2 shows the mapping of the PCI Inter-
face Control Registers. Figure 3–3 shows the mapping of the Board ID Registers. Figure 3–4 shows the mapping of
the Acquisition Control Registers. Figure 3–5 shows the mapping of the Frame Buffer Control Registers. The figures
also give page number references for the register definitions.
The following conventions are used throughout this chapter. The R/W notation following a register or bit name indi-
cates the register or bit supports both read and write access. The R-O notation following a register or bit name indi-
cates the register or bit supports read access only. The W-O notation following a register or bit name indicates the
register or bit supports write access only. The R/W1C notation following a bit name indicates the bit is read for status,
and writing a one clears the bit “write 1 clear”.
NOTE
Upon power–up most of the PCVisionplus registers are in an unknown state. The host CPU must
initialize these registers for proper operation. A system reset affects some but not all of these regis-
ters.
NOTE
Program all reserved bits and registers to zero unless otherwise indicated.
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